JPH0330465U - - Google Patents
Info
- Publication number
- JPH0330465U JPH0330465U JP8919789U JP8919789U JPH0330465U JP H0330465 U JPH0330465 U JP H0330465U JP 8919789 U JP8919789 U JP 8919789U JP 8919789 U JP8919789 U JP 8919789U JP H0330465 U JPH0330465 U JP H0330465U
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- conductor
- interlayer insulating
- edge
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 2
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図〜第３図は本考案の一実施例を示すもの
で、その内第１図は平面図、第２図は第１図のＡ
−Ａ′断面図、第３図は各素子の形状を説明する
ための図面で、同図イ，ロは夫々導体１と下部層
間絶縁層３′についての第２図Ｂ−Ｂ′断面図、
同図ハ，ニは夫々上部導体２と上部層間絶縁層３
″についての第２図Ｃ−Ｃ′断面図である。また
、第４図、第５図は従来例を示すもので、その内
第４図は平面図、第５図は第４図のＡ−Ａ′断面
図である。
１……下部導体、２……上部導体、３′……下
部層間絶縁層、３″……上部層間絶縁層、４……
基板。
Figures 1 to 3 show one embodiment of the present invention, of which Figure 1 is a plan view and Figure 2 is a
-A' cross-sectional view, FIG. 3 is a drawing for explaining the shape of each element, and FIG.
In the same figure, C and D are the upper conductor 2 and the upper interlayer insulating layer 3, respectively.
FIG. 2 is a cross-sectional view taken along the line C-C' of FIG. -A' sectional view. 1... Lower conductor, 2... Upper conductor, 3'... Lower interlayer insulating layer, 3''... Upper interlayer insulating layer, 4...
substrate.
Claims (1)
ハイブリツドＩＣ。 イ 基板。 ロ の基板に対して成膜される下部導体であつて
、上部導体とのクロス相当部分に縁部を設け中心
部に孔を形成した下部導体。 ハ この下部導体のクロス部に上記縁部および孔
を含めて覆うように形成される下部層間絶縁層。 ニ この下部層間絶縁層の上に配置される下部導
体の縁部および孔とほぼ重なり合う縁部と孔とを
備えた上部導体。 ホ この上部導体を埋没するように上記下部層間
絶縁層の上に形成される上部層間絶縁層。[Claims for Utility Model Registration] A hybrid IC characterized by comprising the following elements. A board. (b) A lower conductor to be formed on the substrate, which has an edge at a portion corresponding to the cross with the upper conductor and a hole in the center. (c) A lower interlayer insulating layer formed to cover the cross portion of the lower conductor, including the edge and hole. D. An upper conductor having an edge and a hole that substantially overlaps the edge and hole of the lower conductor disposed on the lower interlayer insulating layer. (e) An upper interlayer insulating layer formed on the lower interlayer insulating layer so as to bury this upper conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8919789U JPH0330465U (en) | 1989-07-31 | 1989-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8919789U JPH0330465U (en) | 1989-07-31 | 1989-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0330465U true JPH0330465U (en) | 1991-03-26 |
Family
ID=31638786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8919789U Pending JPH0330465U (en) | 1989-07-31 | 1989-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0330465U (en) |
-
1989
- 1989-07-31 JP JP8919789U patent/JPH0330465U/ja active Pending