JPH033050A - Memory protecting device - Google Patents

Abstract

PURPOSE:To rapidly execute writing processing by temporarily storing an access address in an exclusive storage means and reading out the contents of a protect memory during the temporary storage of the access address. CONSTITUTION:The protect memory 3 detects an illegal access from the upper several bits of an address bus, an access type and an execution level. When a CPU 1 reads out data written in a data latch but not written in the memory 2, a coincidence detecting circuit 9 detects the status and allows the CPU 1 to read out not the data of the memory 2 but the data of the data latch. When a signal BERR is in the high level, a control circuit 39 controls the data latch so that data writing from the data latch to the memory 2 is not executed to prevent data from being destroyed due to illegal writing. Consequently, waiting time for reading out data from the protect memory 3 can be eliminated and rapid processing can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory protection device. More specifically, the present invention relates to a memory protection device that prevents unauthorized access to computer memory.

2. Description of the Related Art FIG. 5 shows the configuration of a computer equipped with a conventional memory protection device.

The computer shown in FIG. 5 includes a CPU 1 that performs various processes,
Memory 2 stores data associated with CPUI processing, and memory 2 stores addresses where access to memory 2 is prohibited.
When unauthorized access is made to that address,
Protective memory 3 that activates the BERR signal
and a control circuit 50 that controls access made by the CPU to the memory 2. When the CPUI accesses the memory 2, it outputs the address to be accessed to the address bus, and reads the contents of the address via the data bus or writes to the address. At the same time C
The PUI also outputs the type of access to the memory 2 (instruction reading, operand reading, operand writing) and the execution level of the program being executed, to the protection memory 3. The protection memory 3 detects illegal access based on the high-order pinpoint of the address bus, the access type, and the execution level.

The control circuit 50 receives the BCYST (indicating that a bus cycle starts) signal output from the CPUI and the R/W
Signal (indicating whether it is a cycle to read or write memory) and BER output from protect memo U3
In response to the R signal, memory 21; WE double signal, CPUI
A WAIT signal (a signal that causes the CPU to wait until reading or writing to the memory 2 is completed) is output. When the WE multiplication signal output from the control circuit 50 becomes active,
Writing is performed in memory 2.

FIG. 6 shows the operation timing of the calculation film shown in FIG. 5 when writing into the memory. The address bus signal is determined, and the BERR signal is determined after a time tPA (protection memory access time). For the protection function, WE must not be activated against illegal writing, so WE rises after the BERR signal is determined and takes the time required for logic synthesis 1. You will be late.

Problems to be Solved by the Invention The conventional memory protection device described above reads the protection memory when writing data, and outputs a write signal after determining whether access should be permitted. Therefore, there is a drawback that it takes more time than the original processing time.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a memory protection device that solves the problems of the prior art and can quickly perform write processing.

Means for Solving the Problems According to the present invention, in a device for preventing unauthorized access to the memory of a computer, there is provided a first storage means for storing the address of the memory to be protected and the type of unauthorized access; A second storage means for storing data and an address to which the data is written; and a third storage means for storing whether a requested access is permitted; There is provided a memory protection device characterized by comprising a control means for controlling the data stored in the second storage means not to be written to the memory when the second storage means is executed.

Function: The memory protection device of the present invention once performs an access address to a dedicated storage means, and during that time, reads out the protection memory. Therefore, like traditional devices,
Processing speed is improved because there is no need to wait for the protection memory to be read.

EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to Examples, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment 1 FIG. 1 shows a block diagram of a computer equipped with an embodiment of the memory protection device of the present invention.

The computer shown in FIG. 1 includes a CPU 1 that performs various processes,
Consisting of a memory 2 that holds data associated with CPUI processing, a protection memory 3, a latch 6.7.12.13, a tri-state buffer 8.10.11.14, an output circuit 9, and a control circuit 39. A memory protection device is provided.

The protection memory 3 stores an address in the memory 2 that is prohibited from being accessed, and activates the BERR signal when an unauthorized access is made to that address in the memory 2. When the CPUI accesses the memory 2, it outputs the address to be accessed to the address bus, and reads the contents of the address via the data bus or writes to the address. At the same time, the CPU 1 also outputs to the protection memory 3 the type of access to the memory 2 and the execution level of the program being executed. The protection memory 3 detects illegal access from the upper few bits of the address bus, the access type, and the execution level.

CPU 1 and memory 2 are connected via latch 6.7.12.13 and tristate buffer 8.1O111, 14 controlled by control circuit 39.

The control circuit 39 controls the R/W signal output from the CPU l and the V
In response to the BERR signal output from the A-fold signal protection memory 3, the CK-fold signal issued by the clock 4, and the signal E issued by the comparator 9, the WE-fold signal and OE-fold signal are sent to the memory 2, and the 5BT1 signal is sent to the latches 6 and 12. , 5BT2 signal to latches 7 and 11, tri-state buffer 8.
Control signals A, D, C, and B are output on 10.11.14, respectively.

The R/W signal becomes high level when the CPUI performs a read operation, and becomes low level when the CPUI performs a write operation. The VA multiplication signal goes high when the CPU 1 performs a valid write or read operation, and goes low otherwise. Further, data is written into the memory 2 when the WE input terminal is at a high level, and data is read from the memory 2 when the OE input terminal is at a high level.

FIG. 2 shows a circuit diagram of a control circuit 390 of the computer of this embodiment. In the control circuit 39 of this embodiment, the R/W signal is transmitted to the inverters 16, 18, 23, AND gates 32, 33, .
34, VA double signal, inverter 15, AND
Man-powered at gate 20.24.32.33.34.

Also, CK double signal inverter 19.35, AND gate 21.0R-NAND gate 26.27.0R-N
Human power is applied to OR complex gates 28 and 29. The BERR signal is applied to the 0R-NANDI combination gate 26, and the E signal is applied to the AND gate 30. The outputs of inverters 15 and 16 serve as the input power for OR gate 17, and the output of OR gate 17 is input to AND gate 22. The outputs of the inverter 18 and I9 are input to the AND gate 20 together with the VA multiplied signal, and the output of the AND gate 20 is STB.
It is output as one signal.

The output of the inverter 23 is input to the AND gate 24,
The output of the AND gate 24 is input to the inverter 25 and also to the 0R-NANDff1 sum gate 27.

0R-NAND composite gate 26.27.0R-NOR'
The circuit that combines DL gates 28 and 29 includes
The doubled signal BERR signal, the output of AND gate 24 and the output of inverter 25 are input, and the outputs become AND gate 22 and ANDN-gate 30 outputs. AND
The output of the gate 22 becomes a signal and is inputted via an AND gate 21.37, an OR gate 36, and an inverter 38.

The STB2 signal is output from the ΔND game) 21. A
The output of the ND gate 30 is input to the AND gate 32 and the inverter 31, the output of the AND gate 32 is input to the OR gate 36, and the output of the inverter 31 is input to the AND gate 33.
is output to. The B signal is output from the OR gate 36, and
The gate 33 outputs the OE multiplied signal, the AND gate 34 outputs the C and D signals, and the AND gate 37 outputs the WE multiplied signal.

Hereinafter, the operation of a computer equipped with the above-mentioned memory protection device of the present invention will be explained.

First, the bus cycle interface of the CPU 1 will be explained. In the computer of this embodiment, the timing of the bus cycle of the CPU 1 is controlled by the CK multiplier signal input to the clock input terminal. That is, when the CK double signal becomes high level, the bus cycle that was being executed up to that point ends, and the next bus cycle begins. The address, data, R/W signal, VA double signal access type, and execution level output by the CPU are guaranteed to be valid values from a certain time after the CK double signal rises until the next CK double signal rises. Ru.

Furthermore, the data and BERR signal at the time of reading are taken in at the rising edge of the CK signal at the end of the bus cycle.

The operation of the write cycle will be explained below.

CPU l outputs address and data in write cycle, R/W=O1VA=11. :STB 1 signal becomes active when SULT, CK double signal is 0, and latch 6
．． 12, addresses and data are stored. At the same time, the protection memory 3 contains the execution bell, access type,
The upper few bits of the address bus are output. The protection memory 3 stores these signals and the memory 2 that stores them.
If access is prohibited, the BERR signal is set to high level.

If the BERR signal is at a low level, this fact is stored in the control circuit 39. When the next cycle is a read cycle, the write data stored in the latch is left as is, the tri-state buffers 10 and 11 are driven, and the memory is read. The data stored in the latch is written in the next write cycle. In this cycle, first, when CK becomes 1, the data stored in data latch 6.12 is transferred to data latch 7.13, and at the same time tri-state buffer 8.14 is activated and input to memory 2. be done. Subsequently, when CK becomes 0, the address and data output by the CPUI are stored in the latch 6.12, the WE multiplication signal becomes 1, and the data is written into the memory 2.

When the CPU attempts to read data that has been written to the data latch but not written to the memory 2, the -number output circuit 9 detects this and reads the data from the data latch instead of the data from the memory 2. The data is read out by the CPU 1.

When the BERR signal is at high level, the control circuit 39:
Control is performed so that data is not written from the data latch to the memory 2, and data destruction due to unauthorized writing is prevented.

As described above, in the computer memory circuit of the present invention, by temporarily storing data to be written in the memory 2 in the data latch 6.12, the waiting time for reading data in the protection memory 3 is eliminated, and high-speed processing is possible. This is what I did.

Embodiment 2 FIG. 3 shows a block diagram of a computer equipped with a second embodiment of the memory protection device of the present invention.

The memory protection device of this embodiment includes data latches 6.
The main difference from the device of the first embodiment is that a cache memory 40 connected in parallel with 7.12.13 and tristate buffers 8.14 is added.

In the device of this embodiment, data latch 6.7.12.13
Furthermore, there is an advantage that the tri-state buffer 8.14 can also be used as a write buffer for the write-through operation of the cache memory 40. That is, when CPU 1 writes data to memory 2, data latch 6.12
However, on the first day, it receives the address and data and stores it in memory 2.
By passing the data to memory, the CPU 1 can use a short write cycle even for memory that requires a long access time.

The other operations are completely the same as in the first embodiment, so the explanation will be omitted.

Embodiment 3 FIG. 4 shows a block diagram of a computer equipped with a third embodiment of the memory protection device of the present invention.

The memory protection device of this embodiment includes a protection memory 3, a control circuit 39, and a copyback type cache memory 41.

The copy-back type cache memory 41 is
Even if data is written from , it is not written to memory 2 immediately. Therefore, an unauthorized write was made,
When the protect memory 3 sets the BERR signal to high level, the control circuit 39 prevents writing to the memory 2.

In the device of this embodiment, there are many circuits that can be shared by the cache memory and the memory protection device of the present invention, so there is an advantage that the device can be configured with fewer circuits as a whole.

As described in detail, the memory protection device of the present invention includes:
Data is written to the dedicated storage means. Therefore, even if the protection memory is read and data is written at the same time, unauthorized writing can be prevented by stopping writing to the memory from the dedicated latch. Therefore, there is an effect that memory write cycles can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer equipped with an example of the memory protection device of the present invention, FIG. 2 is a block diagram of an example of a control circuit of the device of FIG. 1, and FIG. 4 is a block diagram of a computer equipped with another embodiment of the memory protection device of the invention; FIG. 4 is a block diagram of a computer equipped with still another embodiment of the memory protection device of the invention; FIG. 6 is a block diagram of a computer equipped with a conventional memory protection device, and FIG. 6 is a diagram showing the operation timing of the computer of FIG. 5. [Main reference numbers] 1...CPU, 2...Memory, 3...Protect memory, 4...Clock generation circuit, 6.7...Address latch, 9...-Several structures Output circuit, 10, 11... tri-state buffer, 12, 13
...Data latch, 14...Tri-state buffer, 15, 16.1g, 19.23.25.27.31.
35.38・Inverter, 17, 36・ ・OR gate, 20, 21.22.24.30.32.33.34.3
7AND gate, 26, 27... Composite gate (OR-NAND), 28
, 29... Composite gate (OR-NOR), 39, 5
0...Control circuit, 40, 41...Cache memory.

Claims (1)

[Claims] A device for preventing unauthorized access to memory of a computer, comprising a first storage means for storing an address of the memory to be protected and a type of unauthorized access, and a first storage means for storing data written to the memory and an address at which the data is written. 2 storage means and a third storage means for storing whether the requested access is permitted;
A memory protection device comprising: control means for controlling data stored in the second storage means not to be written to the memory when unauthorized writing is performed on the memory.