JPH0332425U - - Google Patents

Info

Publication number
JPH0332425U
JPH0332425U JP1989092461U JP9246189U JPH0332425U JP H0332425 U JPH0332425 U JP H0332425U JP 1989092461 U JP1989092461 U JP 1989092461U JP 9246189 U JP9246189 U JP 9246189U JP H0332425 U JPH0332425 U JP H0332425U
Authority
JP
Japan
Prior art keywords
package
chip
ring
terminals
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989092461U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989092461U priority Critical patent/JPH0332425U/ja
Publication of JPH0332425U publication Critical patent/JPH0332425U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • H10W72/5473Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この考案の一実施例によるICパツ
ケージの内部配線の一部を示す平面図、第2図は
、従来のICパツケージの内部配線を示す平面図
、第3図は第2図に示すA部の拡大図である。 図において、1……外部端子、2……内部リー
ド群、3……ダイパツト、4……ICチツプ、5
〜12……パツケージの内部リード、13〜20
……ICチツプ端子、21〜23……リング状の
配線である。なお、図中同一符号は同一、または
相当部分を示す。
FIG. 1 is a plan view showing part of the internal wiring of an IC package according to an embodiment of the invention, FIG. 2 is a plan view showing the internal wiring of a conventional IC package, and FIG. 3 is similar to FIG. It is an enlarged view of part A shown. In the figure, 1...external terminal, 2...internal lead group, 3...die pad, 4...IC chip, 5
~12...Package internal lead, 13~20
. . . IC chip terminals, 21 to 23 . . . Ring-shaped wiring. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ICチツプの端子と、パツケージの内部リード
の間にリング状の1本または複数本の配線を付加
することによつて、ピンレイアウトを自由にでき
ることを特徴とするICパツケージ。
An IC package characterized in that the pin layout can be made freely by adding one or more ring-shaped wires between the terminals of the IC chip and the internal leads of the package.
JP1989092461U 1989-08-04 1989-08-04 Pending JPH0332425U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989092461U JPH0332425U (en) 1989-08-04 1989-08-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989092461U JPH0332425U (en) 1989-08-04 1989-08-04

Publications (1)

Publication Number Publication Date
JPH0332425U true JPH0332425U (en) 1991-03-29

Family

ID=31641889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989092461U Pending JPH0332425U (en) 1989-08-04 1989-08-04

Country Status (1)

Country Link
JP (1) JPH0332425U (en)

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