JPH033255A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the wiring resistance without widening wirings and shorten the RC delay time with little increase of the wiring capacitance by using a plurality of adjacent wirings connected in parallel as a signal wiring. CONSTITUTION:A plurality of wirings 3 are connected in parallel between macro cells, function cells, or other cells 1 and 2. When the N number of horizontally adjacent wirings 3 are connected in parallel and used as a signal wiring, the total resistance thereof can be reduced to I/N. The total wiring capacitance does not increase to N times, shortening the RC delay time of the wiring.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a semiconductor integrated circuit device.

(Prior Art) FIG. 6 shows a conventional general semiconductor integrated circuit device, including an inverter, a macro cell such as N0RSNAND,
Or A configured using such macro cells
Functional cells such as DDER and ALU], 2 are connected by wiring 3.

Normally, in such a semiconductor integrated circuit device, as the wiring length increases, the wiring capacitance and wiring resistance increase, so that the signal delay time in the wiring increases. Therefore, when driving a heavy load with long wiring, a transistor with high driving ability is used in the final stage of cells 1.about.2 in FIG. 6 in order to shorten the signal delay time.

Furthermore, in recent years, the geometric size of wiring has become smaller due to higher integration, and the resistance of wiring has increased.
In circuits having long wiring, there are cases where the RC delay of the wiring dominates the signal delay time of the circuit. If the RC delay term of the wiring becomes dominant in the signal delay of the circuit, the operation of the circuit will not become faster no matter how large the driving capacity of the transistor is to drive the wiring load.

Therefore, in conventional semiconductor integrated circuit devices having long wiring, the wiring width is made thicker than that of circuits having short wiring to reduce the wiring resistance and reduce the RC delay time of the wiring. This idea has made it possible to increase the operating speed of the circuit.

(Problem to be Solved by the Invention) However, in a conventional semiconductor integrated circuit device having long wiring, the wiring width is increased to reduce the signal delay time in order to reduce the RC delay time of the wiring. , there were the following problems.

In other words, the wiring for signal propagation from cell to cell is C
This is done by automatic wiring using an AD program, and the wiring pitch P is fixed in order to execute this automatic wiring. For this reason, the wiring width is increased (which may increase the wiring capacitance between adjacent wirings, making it impossible to arbitrarily increase the wiring width and making it impossible to keep the wiring resistance sufficiently small). there were.

This invention was made in view of these conventional problems, and reduces wiring resistance without increasing the wiring width.
An object of the present invention is to provide a semiconductor integrated circuit device that can reduce RC delay time without increasing wiring capacitance so much and can operate at high speed.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor monolithic integrated circuit device of the present invention solves the problem of wiring that is long and is likely to have a long RC delay time due to wiring resistance and wiring capacitance. A plurality of horizontally or vertically adjacent wirings are simultaneously used as signal wirings.

(Function) In the semiconductor integrated circuit device of the present invention, for wiring with a long wiring length, multiple wirings in the horizontal direction N or vertical direction M are simultaneously used as signal lines.
Wiring resistance can be greatly reduced to 1/N or 1/M by connecting multiple N or M wires in parallel, and at the same time, wiring capacitance can be reduced because parallel signal wires operate at the same potential. The inter-wiring capacitance does not increase significantly.

As a result, the RC delay time determined by the product of wiring resistance and wiring capacitance can be effectively shortened.

(Example) Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

FIG. 1 shows a circuit configuration of an embodiment of the present invention, in which a plurality of wiring lines 3, 3, . ... are connected in parallel.

Figure 2 shows a model diagram when the wiring that becomes the signal propagation line is a distributed RC line.If R and C are the total resistance and total capacitance of one wiring 3, respectively, the transmission in Figure 2 is shown. The response v of the receiving end 0T(x-L) when a unit step voltage is applied to the end IN(x-0) (B is expressed by the following formula.

... (].) If we calculate the time t172 until V (t) -1/2 from this formula (1), we get j +/2 -0.381 R C...
(2) becomes.

Therefore, the RC delay time in the wiring 3 can be determined using equation (2).

By the way, when N horizontally adjacent wires 3 (N is an appropriate integer) are connected in parallel and used as signal wires as shown in FIG. 1, the total resistance R of the signal wires is , R'-R/N ・
... It can be reduced to (3).

On the other hand, the wiring capacitance can be considered as follows.

FIG. 3 shows a cross-sectional view of wiring in a circuit of a semiconductor integrated circuit device. Wirings adjacent to the center wiring 3 on the left and right are 347 and 3r, vertically adjacent wirings are 3u and 3d, and the wiring in the center is 347 and 3r. Considering the wiring capacitance of the wiring 3, this is the wiring capacitance C1 with the upper layer wiring 3u and the lower layer wiring 3
d and the wiring capacitance 11C2 with the substrate, and wiring capacitance C3 with the horizontally adjacent wirings 3g and 3r on the left and right.

Therefore, the total linear capacitance C for wiring 3 is C−C
, +C2+2·C3 (4).

The total line capacitance C′ of N wires is usually C′ −N
leprosy C, and the RCC delay time 1/2 of the wiring is t I/2
' -0,381・Ro・C.

= 0.381 ·R−C, which is the same as the RC delay time tl/□ of one wiring.

However, when N adjacent wires are connected in parallel to pass the same signal, each wire operates at the same potential, so there is no need to charge and discharge the capacitance of the adjacent wires.

Therefore, the total line capacitance Cw related to the signal delay time is expressed as C″-N-C, +N-C2+2・C1 −N-C-2・(N-1)・C3...(5) .

The RC delay time of the wiring in this case, 72, is the above (
2), (3), and (4), tl/2 -0.381 ・Ro ・C2 -0,31111-R-C 0,762(N-1) ・R-C3/N...・(
6) From this equation (6), it can be seen that the RC delay time of N wirings is reduced compared to equation (1) in the case of one wiring.

FIG. 4 shows another embodiment of the present invention, in which M lines 3 are arranged adjacent to each other in the vertical direction so that the line capacitance between the upper and lower layers becomes irrelevant to the signal delay time. Therefore, the total wiring resistance is reduced to 1/M times as in the case where the wiring lines 3 are placed adjacent to each other in the horizontal direction as shown in Fig. 1, but the total line capacitance does not increase to M times, and as a result, the wiring The RC delay time becomes smaller.

FIG. 5 shows still another embodiment of the present invention, in which N horizontally adjacent wirings 3 and vertically M adjacent wirings 3 are connected in parallel to form the same signal line. In this embodiment, the wiring capacitance between the left and right, upper and lower layers is made irrelevant to the signal delay time, and the total wiring resistance can be reduced by 1/(N-M) times, and the total line capacitance is N −
It does not increase up to M times, and as a result, the RC delay time of the wiring becomes smaller.

In this way, when multiple wires are connected in parallel so that a large number of adjacent wires are used simultaneously as signal wires, the wire resistance decreases at a greater rate than the wire capacitance increases, and the overall As a result, the RC delay time of the wiring can be reduced. Therefore, even in CAD design where the pitch is constant, a circuit design that does not increase the RC delay time can be achieved by arranging a plurality of wires of a constant width in parallel without increasing the wire width.

In addition, in each of the above embodiments, since a plurality of wiring lines are used as signal lines, it is inevitable that the total line capacitance increases to some extent. For this reason, it takes longer for the transistor that drives the wire to charge and discharge the wire capacitance, and if too many wires are placed adjacent to each other, the signal delay time may become longer than with a single wire. It's possible.

Therefore, the number of adjacent wires must be determined so as not to increase the overall signal delay time, and is usually 2.
, , are preferably connected adjacently in parallel as signal lines in order to simplify the circuit configuration.

[Effects of the Invention] As described above, according to the present invention, since a plurality of adjacent wirings are connected in parallel and used as signal wirings, the wiring capacitance increases due to the plurality of wirings. Since the wiring resistance is reduced by more than the increase, the RC delay time can be reduced even in the case of automatic wiring using CAD in which the wiring pitch is fixed, and the circuit operation can be speeded up.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a single cell example of the present invention, Fig. 2 is a model diagram when the wiring serving as the signal propagation line in the above embodiment is a distributed RC line, and Fig. 3 is another embodiment of the invention. An example circuit diagram, FIG. 4, is a circuit diagram of still another embodiment of the present invention, FIG.
This figure is a circuit diagram of yet another embodiment of the present invention, and FIG. 6 is a circuit diagram of a conventional example. 12...Cell 3...Wiring

Claims (1)

[Claims] A semiconductor integrated circuit device characterized in that a plurality of horizontally or vertically adjacent wirings are connected in parallel and used simultaneously as signal wirings.