JPH0590409A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the area of an interconnection region in a semiconductor integrated circuit. CONSTITUTION:Macro-blocks 11-14 in a semiconductor integrated circuit having a polysilicon later and two aluminum layers are formed of polysilicon and a first aluminum interconnection. Macro-blocks 11-14 are interconnected without intersections through second aluminum interconnections 18-24 through input/ output terminals 16, which are porvided in the insides of the macro-blocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a polysilicon gate C using multi-layer metal wiring.
The present invention relates to a wiring structure of a MOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional semiconductor integrated circuit having one layer of polysilicon and two layers of aluminum (hereinafter referred to as aluminum). Here, the circuit blocks 11 to 14 forming the integrated circuit are called macro blocks, and are blocks obtained by dividing the entire circuit into functional units. Although these macro blocks 11 to 14 are composed of basic logic blocks such as NAND and NOR, the wiring layers used are only polysilicon wiring and the first aluminum wiring.
The input / output terminal 16 is provided by the second aluminum wiring on two parallel sides of the macro blocks 11-14.

The integrated circuit is completed by connecting the macro blocks 11 to 14, but since the wiring between the macro blocks has a length of several mm, the first aluminum wiring and the second aluminum wiring having a small resistance are used. It is used to suppress the signal delay. In the figure, a lead wire 41 from the input / output terminals 16 of the macro blocks 11 to 14 or a wire 42 between macro blocks in the same direction as the lead wire 41 is a second aluminum wire, and a wire in a direction orthogonal to the lead wire 41. 43
Is the first aluminum wiring, and wiring in these two directions is
Macro block 1 by connecting with the second aluminum contact 44
Connect between 1-14.

At this time, since the first aluminum wiring is used inside the macro blocks 11-14, the first aluminum wiring 43 between the macro blocks passes between the macro blocks 11-14. In addition, since the second aluminum wiring is not used inside the macro blocks 11 to 14, the wiring 45 that goes to the opposite side of the macro block is passed over the macro block 14 by using the second aluminum wiring to shorten the wiring length. To do.

[0005]

In the wiring of the conventional semiconductor integrated circuit, the second aluminum wiring used for wiring between the macroblocks is the lead-out wiring 41 from the input / output terminal 16, so the amount used is small and the wiring is small. Is mostly the first aluminum wiring. Since the first aluminum wiring is used inside the macro block, most of the wiring between macro blocks is empirically about 50 to 75% of the whole area as a wiring area different from the macro block. However, there was a problem that

An object of the present invention is to solve the above problems and to provide a semiconductor integrated circuit in which the wiring area of the integrated circuit is reduced by appropriately distributing the wiring region.

[0007]

The structure of the present invention comprises polysilicon as a wiring layer and a plurality of metal wiring layers, and each macroblock is formed by a wiring layer other than the metal wiring layer among these metal wiring layers. In the connected semiconductor integrated circuit,
The input / output terminal of each macroblock is connected to the uppermost metal wiring layer, and at least one metal wiring layer is connected from the input / output terminal to each of the surrounding macroblock regions, thereby forming each macroblock. The input / output terminals are connected by the uppermost metal wiring layer alone.

[0008]

1 is a block diagram of a semiconductor integrated circuit for explaining an embodiment of the present invention. This integrated circuit has a polysilicon layer as a wiring layer, a first aluminum wiring, and a second aluminum wiring, and is made by connecting four macro blocks 11 to 14 to each other by the second aluminum wiring. Macro block 1
1 to 14 are polysilicon layers as internal wiring layers,
Made using only aluminum wiring, and I / O terminal 16
Is a second aluminum wiring layer and is arranged inside the macroblock with an area through which at least one second aluminum wiring can pass.

The macro blocks 11 to 14 are arranged at the minimum interval between the patterns in the macro block, and the power supply wiring 17 is wired by the first aluminum wiring. The wiring between the terminals of the macro blocks 11 to 14 is performed by vertically or horizontally running on the macro block by the second aluminum wiring.

In this integrated circuit, the connection between macro blocks is made by wiring 18 from macro block 11 to macro block 12, wiring 19 from macro block 11 to macro block 13, wiring 20 from macro block 11 to macro block 14, and macro. Wiring 21 from block 12 to macroblock 13, Wiring 22 from macroblock 12 to macroblock 14, Macroblock 13
From the macro block 14 to the macro block 14, and from the macro block 11 to the macro block 12, the macro block 13, and the macro block 14, there are 7 routes. Wiring can be done in a single layer of wiring.

FIG. 2 is a block diagram for explaining another embodiment of the present invention. This semiconductor integrated circuit is a circuit which is composed of five macro blocks 11 to 15 and has a wiring of one layer of polysilicon and three layers of aluminum wiring.
Signal wirings inside 1 to 15 and between macro blocks 11 to 15 are connected using a polysilicon layer, a first aluminum wiring layer and a second aluminum wiring layer.

This semiconductor integrated circuit has a power supply (V _DD ) pad 31, an installation (GND) pad 32, and one current supply terminal, and supplies power to five macro blocks 11 to 15.

Here, the macro block 15 is a special circuit that separates the power supply wiring from the other macro blocks 11 to 14, and widens the wiring width of the first VDD wiring 33 and the first GN.
The D wiring 32 passes over the macro block and is connected to the power wiring in the macro block 15 by the contact 36. The macro blocks 11 to 14 are connected to the second V which is a common power supply wiring.
Power is supplied by the _DD wiring 32 and the second GND wiring 34.

[0014]

As described above, according to the present invention, the input / output terminals of the macroblock using the polysilicon layer and the first aluminum layer as wiring are placed inside the macroblock, and the wiring between the macroblocks is connected to the second aluminum. Layers are used to run vertically or horizontally on the macroblocks and connect without crossing each other, so that the area only for inter-macroblock wiring can be reduced to 30% or less of the entire area, and the area of the semiconductor integrated circuit can be reduced. The effect is that it can be made smaller. Further, the power supply wiring to be supplied to the macro block can be freely connected on the macro block by the second aluminum layer, and the plurality of power supply wirings,
Since power wirings of arbitrary thickness can be wired on the macroblock without crossing each other, there is an effect that an increase in area due to the power wiring area and an increase in resistance due to wiring crossing can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional IC wiring.

[Explanation of symbols]

11-14, 15 macroblock 16 input / output terminal (second aluminum) 17 power supply wiring (first aluminum) 18 block 11-12 wiring (second aluminum) 19 11-13 wiring 20 11-14 wiring 21 12 -13 wiring 22 12-14 wiring 23 13-14 wiring 24 11-14 wiring 31 V _DD pad 32 GND pad 33, 34 VDD wiring 35, 36 GND wiring 37 contact 41 terminal lead wire 42, 43 macroblock Inter-wiring 44 First and second aluminum contacts 65 Passing wiring

Claims (2)

[Claims] 1. A semiconductor integrated circuit comprising polysilicon and a plurality of metal wiring layers as a wiring layer, wherein each macro block is connected by a wiring layer other than the metal wiring layer among the metal wiring layers. The input / output terminals of the block are connected to the uppermost metal wiring layer, and at least one metal wiring layer is connected from the input / output terminal to each of the surrounding macroblock regions, thereby inputting / outputting the macroblocks. A semiconductor integrated circuit, wherein terminals are connected by the uppermost metal wiring layer alone. 2. The semiconductor integrated circuit according to claim 1, wherein the terminals on the macroblocks are power supply terminals, and the power supply wiring between these macroblocks is connected in the uppermost layer.