JPH0332836U - - Google Patents
Info
- Publication number
- JPH0332836U JPH0332836U JP9041489U JP9041489U JPH0332836U JP H0332836 U JPH0332836 U JP H0332836U JP 9041489 U JP9041489 U JP 9041489U JP 9041489 U JP9041489 U JP 9041489U JP H0332836 U JPH0332836 U JP H0332836U
- Authority
- JP
- Japan
- Prior art keywords
- high frequency
- emitter
- power supply
- frequency signals
- switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の高周波信号切替え回路の実施
例を示す回路図である。
FIG. 1 is a circuit diagram showing an embodiment of the high frequency signal switching circuit of the present invention.
Claims (1)
出力信号３を得る機器において、個個の入力高周
波信号１，２を、ベースを整合抵抗４，５を介し
て接地し、コレクターをプラス電源６に、エミツ
ターを抵抗７８及びこれに直列接続されたスイツ
チングトランジスター９，１０を介してマイナス
電源１１に接続したエミツターホロワー１２，１
３を介し、そのオン、オフ 制御入力１４，１５
を、前記スイツチングトランジスター８，９のオ
ン、オフ入力になる如く接続されたアナログスイ
ツチ１６，１７の入力側１８，１９に接続し、そ
のアナログスイツチの出力２０，２１を共通接続
し整合アンプ２２を介して出力３に出力する如く
構成し、前記エミツターホロワー１２１３のエミ
ツターに、前記スイツチングトランジスター９，
１０がオフ時に逆バイアスが掛かるようにバイア
ス抵抗２３，２４，２５，２６を設けた高周波信
号切替え回路。 In a device that switches a plurality of input high frequency signals 1 and 2 to obtain one output signal 3, the bases of the individual input high frequency signals 1 and 2 are grounded through matching resistors 4 and 5, and the collectors are connected to a positive power supply 6. , an emitter follower 12,1 whose emitter is connected to a negative power supply 11 via a resistor 78 and switching transistors 9,10 connected in series thereto.
3, its on and off control inputs 14, 15
are connected to the input sides 18 and 19 of analog switches 16 and 17 which are connected so as to be the ON/OFF inputs of the switching transistors 8 and 9, and the outputs 20 and 21 of the analog switches are connected in common to a matching amplifier 22. The emitter follower 1213 has an emitter connected to the switching transistor 9,
A high frequency signal switching circuit provided with bias resistors 23, 24, 25, and 26 so that a reverse bias is applied when 10 is off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9041489U JPH0332836U (en) | 1989-08-02 | 1989-08-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9041489U JPH0332836U (en) | 1989-08-02 | 1989-08-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332836U true JPH0332836U (en) | 1991-03-29 |
Family
ID=31639936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9041489U Pending JPH0332836U (en) | 1989-08-02 | 1989-08-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332836U (en) |
-
1989
- 1989-08-02 JP JP9041489U patent/JPH0332836U/ja active Pending