JPH0334025B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage drop detection reset circuit that generates a reset signal for a certain period of time using a delay circuit when input power is turned on, and thereafter detects a drop in input power supply voltage and generates a reset signal. This invention relates to a voltage drop detection reset circuit that does not require adjustment.

FIG. 1 is a block diagram of a conventional voltage drop detection reset circuit, and FIG. 2 shows the Zener voltage/current characteristics of a Zener diode. 1 in the figure is a comparison circuit,
2 is an AND circuit, V is the power supply voltage, R ₁₁ to _{R 13} are resistors,
_R14 is a variable resistor, D is a Zener diode, _C4 ,
_C5 is a capacitor. In operation, when the input power is turned on, a delay circuit consisting of resistor _R11 and capacitor _C4 causes the output of AND circuit 2 to be "0", that is, generate a reset signal, until the potential of capacitor _C4 reaches a certain voltage. There is. On the other hand, the Zener voltage of the Zener diode D and the power supply voltage V are connected to the resistor
The voltage divided by R ₁₂ and R ₁₃ is connected to the comparator circuit 1.
If the power supply voltage V decreases, the comparator circuit 1
The output of is “0” and the output of AND circuit 2 is “0”
That is, a reset signal is generated. However, the characteristics of the Zener voltage of the Zener diode D vary from element to element as shown in Figure 2, and in order to obtain a constant Zener voltage, the Zener current must be controlled by a variable resistor for each element.
There is a drawback that R ₁₄ must be adjusted and varied.

SUMMARY OF THE INVENTION An object of the present invention is to provide a voltage drop detection reset circuit that does not require adjustment of the reference voltage circuit in order to eliminate the above-mentioned drawbacks.

The above purpose consists of a transistor Q ₁ , a resistor R ₂ and a capacitor C ₂ connected in parallel to the base of the transistor Q ₁ , and when the input power is applied to the emitter of the transistor Q ₁ , the transistor Q ₁ The potential when the input power supply voltage is turned on and the input power supply voltage becomes normal is stored in the capacitor _C2 , and when the input power supply voltage drops below the base potential of the transistor _Q1 or is cut off, the voltage drop that turns off the transistor _Q1 . It is connected between the detection means and a buffer circuit consisting of the collector of transistor Q ₁ and transistors Q ₃ and Q ₄ , and when the input power is turned on, after generating a reset signal for a certain period of time, the output of the buffer circuit is set to high level, and the input power is turned on. This problem is solved by the voltage drop detection reset circuit of the present _invention , which includes a delay circuit that generates a reset signal and immediately brings the output of the buffer circuit to a low level when the voltage drops below the base potential of the transistor Q1 or is cut off.

An embodiment of the present invention will be described below with reference to the drawings. Fig. 3 shows a voltage drop detection reset circuit according to an embodiment of the present invention, and Fig. 4 shows a time chart of A in Fig. 3.
indicates the power supply voltage and the base potential of the transistor _Q1 , B indicates the potential at point a, and C indicates the reset output of the output terminal 3. In the diagram, R ₁ to R ₁₀ are resistances, C ₁ to _{C 3}
is a capacitor, _Q1 to _Q4 are transistors, V is a power supply voltage, 3 is a reset signal output terminal, a, b, c
indicates an illustrative point. As for the configuration of each element, a ripple filter for the power supply voltage V is formed by a resistor R _and a capacitor _C1 , and fluctuations in the power supply voltage V due to noise etc. are absorbed to maintain stable operation of this circuit. A decrease in the power supply voltage V is detected by the transistor Q ₁ , the resistor R ₂ , and the capacitor C ₂ . diode _D1 ,
Capacitor C ₃ and resistor R ₃ constitute a delay circuit when power is turned on. Transistor Q ₂ , resistor R ₇
The charge in capacitor _C3 is discharged. A buffer is formed by transistor Q ₃ Q ₄ and resistor R ₈ R ₉ R ₁₀ . First, we will explain when the power is turned on. When the power is turned on, a voltage is applied to the emitter of transistor _Q1 via resistor _R1 . At that time, since the charge in capacitor C ₂ is zero, sufficient voltage is applied between the base and emitter of transistor Q ₁ and transistor Q ₁ is turned on, so that a voltage appears at the collector of transistor Q ₁ . However, since the charge of capacitor C ₃ is zero, the current is resistor R ₃ ,
The current flows through the diode D ₁ and the capacitor C ₃ , and the charge accumulates in the capacitor C ₃ , causing the voltage of the capacitor C ₃ to rise. That is, the potential at point a rises as shown in FIG. 4B. However, until the voltage of capacitor C ₃ rises, the base voltage of transistor Q ₃ is small and transistor Q ₃ is off and transistor Q ₄ is on. Therefore, the output from the output terminal 3 is at a low level, and a reset signal is output as shown in FIG. 4C. Eventually, when enough charge is accumulated in the capacitor _C3 , the potential at point a becomes high, the base voltage of the transistor _Q3 also rises, and the transistor _Q3 turns on.
As a result, the transistor _Q4 is turned off, so that the output of the output terminal 3 becomes high level and the reset signal is released. During this time, current also flows to the base of transistor _Q1 and charges capacitor _C2 , as shown in Figure 4A.
As shown in FIG. ₂ , the base potential of the transistor Q1 is a constant potential that is a constant voltage lower than the power supply voltage V determined by the upstream transistor _Q1 . Next, the operation when the power supply voltage drops will be explained. Normally, current flows through the resistor R ₂ to the base of the transistor Q ₁ and the transistor Q ₁ is turned on. Therefore a
Although the potential at the point is high, when the power supply voltage begins to drop as shown in b in Figure 4 A, if the time constant of capacitor C ₂ and resistor R ₂ is made longer than the time constant for the power supply voltage to drop, the base of transistor Q ₁ Since the potential is considered to be constant _, the voltage between the base and emitter of transistor Q ₁ decreases by the amount _that the emitter voltage of transistor Q ₁ decreases. Q ₁ is off.
Therefore, the potential at point a decreases and the base voltage of transistor _Q3 also decreases, transistor _Q3 is turned off, transistor _Q4 is turned on, and the output of output terminal 3 becomes low level, outputting a reset signal.
At the same time, the base potential of the transistor _Q2 also decreases, so the voltage between the base and emitter of the transistor _Q2 increases and the transistor _Q2 turns on. Therefore, the charge of capacitor C ₃ is resistor R ₇
is discharged through. Therefore, the potential at point a decreases as shown in FIG. 4B. After that, the power supply voltage V rises, and the emitter voltage of transistor _Q1 becomes higher than the base potential of transistor _Q1 .
When the voltage rises above a certain high value determined by _Q1 , the transistor _Q1 turns on and outputs a reset signal until a sufficient charge is accumulated in the capacitor _C3 and the potential at point a rises as described above. As explained above, the potential when the power supply voltage V is in the normal state is stored in the capacitor _C2 , and this potential is compared with the power supply voltage V to detect a drop in the power supply voltage V, so a special standard is used. No voltage is required, so there is no need to adjust it for each element. In this circuit, even when the power supply voltage V drops due to a momentary interruption or the like and then recovers, the reset is released after a delay time by the resistor R ₃ , diode D ₁ , and capacitor C ₃ . In this circuit, the buffer circuit uses transistors Q ₃ Q ₄ , so if the power supply is cut off and the power supply voltage V drops considerably, an unstable signal as shown at point c in Figure 4 C may be generated. But this difference is the power supply voltage V
There is no problem because the voltage has dropped considerably and the equipment connected to the output terminal 3 does not operate at this power supply voltage V. However, if the operation when the power supply voltage V drops to a certain extent (higher than the power supply voltage corresponding to point c) is not a problem, an IC may be used in place of the transistors Q ₃ Q ₄ . In addition, if a certain time delay is required whenever the power supply voltage V drops due to a momentary interruption of the power supply voltage V, etc., a thyristor can be used in place of the transistor _Q2 , and the charge can be maintained until the charge in the capacitor _C3 is completely eliminated. , a certain delay time can be obtained.

As described in detail above, the present invention has the effect of providing a voltage drop detection reset circuit that does not require a special reference voltage circuit and therefore does not require adjustment of reference voltage elements.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional voltage drop detection reset circuit, Fig. 2 is a Zener voltage/current characteristic of a Zener diode, Fig. 3 is a voltage drop detection reset circuit of an embodiment of the present invention, and Fig. 4 is a block diagram of a voltage drop detection reset circuit of a conventional example. In the time chart in Figure 3, A is the power supply voltage and transistor.
Q indicates the base potential of ₁ , B indicates the potential of point a,
C indicates the reset output of output terminal 3. In the figure, 1 is a comparison circuit, 2 is an AND circuit, 3 is a reset signal output terminal, V is a power supply voltage, R ₁ to _{R 13} are resistors, R ₁₄ is a variable resistor, D is a Zener diode, D ₁ is a diode, C ₁ ~ _C5 is a capacitor, _Q1 ~ _Q4 are transistors, and a, b, and c are points for explanation.

Claims (1)

[Claims] 1. A transistor Q ₁ , a resistor R ₂ and a capacitor C ₂ connected in parallel to the base of the transistor Q ₁ .
When the input power applied to the emitter of the transistor Q ₁ is turned on, the transistor Q ₁
The potential when the input power supply voltage is turned on and the input power supply voltage is in a normal state is stored in the capacitor _C2 , and when the input power supply voltage becomes lower than the base potential of the transistor _Q1 or is cut off, the transistor _Q1 is turned off. voltage drop detection means that turns off the collector of the transistor _Q1 and the transistor
Connected between the buffer circuit consisting of Q ₃ and Q ₄ ,
When the input power supply is turned on, a reset signal is generated for a certain period of time, and then the output of the buffer circuit is set to a high level, and when the input power supply voltage drops below the base potential of the transistor _Q1 or is cut off, a reset signal is generated and the buffer circuit is turned off. 1. A voltage drop detection reset circuit comprising: a delay circuit that immediately brings the output of the circuit to a low level.