JPS6013629B2 - Control signal receiving circuit - Google Patents

Control signal receiving circuit

Info

Publication number
JPS6013629B2
JPS6013629B2 JP14500479A JP14500479A JPS6013629B2 JP S6013629 B2 JPS6013629 B2 JP S6013629B2 JP 14500479 A JP14500479 A JP 14500479A JP 14500479 A JP14500479 A JP 14500479A JP S6013629 B2 JPS6013629 B2 JP S6013629B2
Authority
JP
Japan
Prior art keywords
circuit
voltage
control signal
level
becomes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14500479A
Other languages
Japanese (ja)
Other versions
JPS5668045A (en
Inventor
敏夫 下山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP14500479A priority Critical patent/JPS6013629B2/en
Publication of JPS5668045A publication Critical patent/JPS5668045A/en
Publication of JPS6013629B2 publication Critical patent/JPS6013629B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset
    • H04L25/062Setting decision thresholds using feedforward techniques only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Selective Calling Equipment (AREA)

Description

【発明の詳細な説明】 本発明は、テレメータ装置、ダム放流警報装置など、監
視装置からの遠隔制御信号を受信するメカニカルフィル
夕を使用した受信回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving circuit using a mechanical filter for receiving a remote control signal from a monitoring device such as a telemeter device or a dam discharge alarm device.

従来この種の回路は、第1図に示すように構成されてお
り、図において1は制御信号の入力端子、2は入力様子
1からの制御信号を増幅する増幅器、3は受信する制御
信号の周波数にのみ惑鉱区するメカニカルフィル夕、4
はこのメカニカルフィル夕3からの出力を増幅する増幅
器、5は増幅器4からの交流電圧を直流電圧に変換する
整流回絡、6は整流回路5からの直流電圧を波形整形す
るシュミットトリガ回路、7は出力端子である。ここで
従来の回路の欠点を説明するためメカニカルフィル夕の
特性を第2図a,bおよびcに示す。メカニカルフィル
夕3に第2図aに示す時間Tの長さだけ信号が加わると
、その応答波形は第2図bに示す波形となる。これを増
幅器4で増幅し、整流回路5で整流すると第2図cに示
す波形となる。このメカニカルフィル夕3の応答波形に
は、第2図bの8に示すような残留特性があるため、第
2図cの波形も同様に9となる。そこで第1図のシュミ
ットトリガ回路6のトリガレベルを第2図cの10‘こ
示すようにレベル11としベル12の間に調整すれば出
力様子7には第2図dに示す時間tの波形が出力するが
、もし、このトリガレベルを第3図aに示すようにレベ
ル13に調整すると、出力聡子7は第3図bに示す時間
t,の波形となる。また、トリガレベルを第4図aに示
すようにレベル14に調整すると、出力様子7は第4図
bに示す時借地の波形となる。このようにトリガレベル
によって出力時間tが変化するということは、トリガレ
ベルが一定でも、入力信号レベルが変化すれば同機に出
力時間tが変化することになる。すなわち、入力端子1
からの制御信号レベルが大きくなって、トリガレベルが
第3図aに示すように相対的にレベル13と同じになっ
た場合、出力端子7の波形は第3図b‘こ示すt,とな
る。また逆に入力端子1からの制御信号レベルが小さく
なって、トリガレベルが4図aに示すように相対的にレ
ベル14となった場合、出力端子7の波形は第4図bに
示すらとなる。このように制御信号の入力時間Tに対し
て出力時間tは入力レベルが変動すると第3図bのt,
や第4図bのりこ示すようになり、出力時間の許容範囲
を越える事がある。
Conventionally, this type of circuit is constructed as shown in Fig. 1, in which 1 is an input terminal for a control signal, 2 is an amplifier for amplifying the control signal from the input state 1, and 3 is an amplifier for receiving the control signal. Mechanical filter that is only sensitive to frequency, 4
is an amplifier that amplifies the output from the mechanical filter 3; 5 is a rectifier circuit that converts the AC voltage from the amplifier 4 into a DC voltage; 6 is a Schmitt trigger circuit that shapes the waveform of the DC voltage from the rectifier circuit 5; 7 is the output terminal. In order to explain the drawbacks of the conventional circuit, the characteristics of the mechanical filter are shown in FIGS. 2a, b and c. When a signal is applied to the mechanical filter 3 for the length of time T shown in FIG. 2a, the response waveform becomes the waveform shown in FIG. 2b. When this is amplified by the amplifier 4 and rectified by the rectifier circuit 5, a waveform shown in FIG. 2c is obtained. Since the response waveform of the mechanical filter 3 has a residual characteristic as shown at 8 in FIG. 2b, the waveform in FIG. 2c also becomes 9. Therefore, if the trigger level of the Schmitt trigger circuit 6 in FIG. 1 is adjusted to level 11 as shown at 10' in FIG. However, if this trigger level is adjusted to level 13 as shown in FIG. 3a, the output Satoko 7 will have a waveform at time t shown in FIG. 3b. Further, when the trigger level is adjusted to level 14 as shown in FIG. 4a, the output state 7 becomes the waveform of the timer as shown in FIG. 4b. The fact that the output time t changes depending on the trigger level in this way means that even if the trigger level is constant, the output time t of the same aircraft will change if the input signal level changes. That is, input terminal 1
When the level of the control signal from the output terminal increases and the trigger level becomes relatively equal to level 13 as shown in Figure 3a, the waveform of the output terminal 7 becomes t as shown in Figure 3b'. . Conversely, when the control signal level from input terminal 1 becomes small and the trigger level becomes relatively level 14 as shown in Figure 4a, the waveform of output terminal 7 becomes as shown in Figure 4b. Become. In this way, when the input level changes, the output time t with respect to the input time T of the control signal is t in Fig. 3b,
The output time may exceed the allowable range as shown in Figure 4b.

このため、制御信号の伝送回線が周波数特性などのため
にレベル変動が大きい場合には第1図の回路では増幅器
2にAGC回路を付加する必要がある。しかし、AGC
回路を付加すると音声などの雑音で誤動作しやすいとい
う欠点があり、さらにメカニカルフィル夕の個々の特性
にばらつきがあるため、たとえAGC回路につけても増
幅器4でレベル調整をしなければならない煩雑さがあっ
た。本発明はメカニカルフィル夕の残留特性やレベル特
性の影響をなくし、さらに伝送回線でのレベル変動に対
してAGC回路がなくても無調整でレベルマージンを大
きくするために、入力信号のピーク値をホールドし、そ
のピーク値に応じてシュミットトリガ回路のトリガレベ
ルを自動的に調整するようにしたもので、以下図面を用
いて詳細に説明する。
Therefore, if the control signal transmission line has large level fluctuations due to frequency characteristics or the like, it is necessary to add an AGC circuit to the amplifier 2 in the circuit shown in FIG. However, A.G.C.
Adding a circuit has the disadvantage that it is prone to malfunction due to noise such as voices, and since the characteristics of each mechanical filter vary, even if it is attached to the AGC circuit, it is complicated to adjust the level with amplifier 4. there were. The present invention eliminates the influence of residual characteristics and level characteristics of a mechanical filter, and further increases the level margin without adjustment even without an AGC circuit in response to level fluctuations in a transmission line by adjusting the peak value of an input signal. The trigger level of the Schmitt trigger circuit is automatically adjusted according to the peak value held, and will be explained in detail below with reference to the drawings.

第5図は本発明の制御信号受信回路の実施例のブロック
図で、1〜7は第1図に相応し、本発明の特徴とすると
ころは整流回路5とシュミットトリガ回路6の間にピー
クホールド回路15、ダイオードスイッチ回路16を設
けたことにある。
FIG. 5 is a block diagram of an embodiment of the control signal receiving circuit of the present invention, numbers 1 to 7 correspond to FIG. This is because a hold circuit 15 and a diode switch circuit 16 are provided.

第6図はこのピークホールド回路15、ダイオードスイ
ッチ回路16およびシュミットトリガ回路6の結線図で
、増幅器A,、抵抗欠,,R2,R3,R4、ダイオー
ドCO.およびコンデンサC,とによりピークホールド
回路15を構成し、増幅器ん、ダイオードDC2抵抗R
5でダイオードスイッチ回路16を構成し、端子18か
らトリガレベルの最小値としての基準電圧を加える。次
に第6図および第7図を用いてその動作を説明する。
FIG. 6 is a wiring diagram of the peak hold circuit 15, diode switch circuit 16, and Schmitt trigger circuit 6, with amplifier A, resistor missing, R2, R3, R4, diode CO. and capacitor C, constitute a peak hold circuit 15, amplifier N, diode DC2 resistor R
5 constitutes a diode switch circuit 16, and a reference voltage as the minimum value of the trigger level is applied from a terminal 18. Next, the operation will be explained using FIGS. 6 and 7.

端子17に整流回路5から直流変換された電圧が加わる
と抵抗戊,,R2で分圧された縄圧が増幅器A,の由側
入力端子に加わり、ダイオ−ドCO.が導通して抵抗R
3を介してコソデンサC,に充電される。充電に要する
時間は抵抗R3とコンデンサC,の値で決まるが、この
時定数より十分長く入力電圧が加えられればコソデンサ
C,には抵抗虫,,R2で分圧したピーク電圧まで充電
される。しかし、入力電圧が減少した場合にはダイオー
ドCD,で電流が制限されるためコンデンサC,の電圧
はピーク値をホールドすることになる。ホールドする時
間はコンデンサC,の値と抵抗R3,R4の値で決めら
れ、放電時定数は第7図aのt3より充分長く選んであ
る。また、ダイオードCD,が非導通となった時、増幅
器んの■側入力端子に加わる電圧はコソデンサC,の電
圧を抵抗R3,R4で分圧した電圧となるが、抵抗R4
は抵抗R3より十分大きいものとすれば抵抗戊4による
電圧降下は無視できる。そこでコンデンサC,の電圧が
増幅器A2の由側入力端子に加わる時、端子18からの
基準電圧より大きい場合にはダイオードCD2は導通し
てスイッチ回路16の出力電圧はコンデンサC,の電圧
となる。逆にコンデンサC,の電圧が基準電圧より小さ
い場合にはダイオードCD2は非導通となるのでスイッ
チ回路16の出力電圧は基準電圧となる。このスイッチ
回路16の出力電圧がシュミットトリガ回路6のトリガ
レベルで、端子17からの電圧がトリガレベルより大き
いときはシュミットトリガ回路6の出力はHレベルとな
り、端子!7からの電圧がトIJガレベルより小さいと
きは、シュミットトリガ回路6の出力はLレベルとなる
When the DC-converted voltage from the rectifier circuit 5 is applied to the terminal 17, the voltage divided by the resistors 1 and 2 is applied to the input terminal of the amplifier A, and the diode CO. becomes conductive and the resistance R
3, the capacitor C is charged. The time required for charging is determined by the values of resistor R3 and capacitor C, but if input voltage is applied for a period sufficiently longer than this time constant, capacitor C will be charged to the peak voltage divided by resistor R2. However, when the input voltage decreases, the current is limited by the diode CD, so the voltage across the capacitor C will be held at its peak value. The holding time is determined by the value of the capacitor C and the values of the resistors R3 and R4, and the discharge time constant is selected to be sufficiently longer than t3 in FIG. 7a. Furthermore, when the diode CD becomes non-conductive, the voltage applied to the input terminal on the side of the amplifier becomes the voltage obtained by dividing the voltage of the capacitor C by the resistors R3 and R4.
Assuming that R is sufficiently larger than resistor R3, the voltage drop due to resistor R4 can be ignored. Therefore, when the voltage of the capacitor C is applied to the input terminal of the amplifier A2, if it is larger than the reference voltage from the terminal 18, the diode CD2 becomes conductive and the output voltage of the switch circuit 16 becomes the voltage of the capacitor C. Conversely, when the voltage of the capacitor C is lower than the reference voltage, the diode CD2 becomes non-conductive and the output voltage of the switch circuit 16 becomes the reference voltage. When the output voltage of this switch circuit 16 is the trigger level of the Schmitt trigger circuit 6 and the voltage from the terminal 17 is higher than the trigger level, the output of the Schmitt trigger circuit 6 becomes H level, and the terminal! When the voltage from 7 is lower than the IJ level, the output of the Schmitt trigger circuit 6 becomes L level.

今、端子17に第7図aの実線で示した電圧が加わった
場合、シュミットトリガ回路6のトリガレベルは第7図
aの点線で示したようになる。ここで19の蟹圧は端子
18から与えられる基準電圧でトリガレベルの最小値と
なる。入力端子17の電圧がA点でトリガレベルより大
きくなると出力端子7は第7図bのようにHレベルとな
る。
Now, when the voltage shown by the solid line in FIG. 7a is applied to the terminal 17, the trigger level of the Schmitt trigger circuit 6 becomes as shown by the dotted line in FIG. 7a. Here, the crab pressure of 19 is the reference voltage applied from the terminal 18 and is the minimum value of the trigger level. When the voltage at the input terminal 17 becomes higher than the trigger level at point A, the output terminal 7 becomes H level as shown in FIG. 7b.

さらに入力電圧が大きくなるとB点でスイッチ回路16
のダイオードCD2が導通してトリガレベルは入力電圧
を抵抗R,,R2で分圧した電圧となる。C点で入力電
圧が小さくなるとトリガレベルはピークホールド回路1
5によって保持される。D点で入力電圧がトリガレベル
より小さくなると、出力端子7はLレベルとなる。第7
図aの21のようなメカニカルフィル夕3の残留特性の
山部分があってもトリガレベルは第7図aの20のよう
にまだ十分保持されているのでシュミットトリガ回路6
の出力は反転しない。ピークホールド回賂15のコンデ
ンサC,が放電を完了すればトリガレベルは基準蚤圧と
なり19の状態にもどる。このように制御信号の入力時
間すなわち第7図aのTに対して出力時間は第7図bの
Lとなり、入力レベルが過大となっても第3図bのよう
に出力時間が伸びることはなくし‘まほとんど変動しな
い。
When the input voltage increases further, the switch circuit 16 at point B
The diode CD2 becomes conductive, and the trigger level becomes a voltage obtained by dividing the input voltage by the resistors R, , R2. When the input voltage decreases at point C, the trigger level changes to peak hold circuit 1.
Retained by 5. When the input voltage becomes smaller than the trigger level at point D, the output terminal 7 becomes L level. 7th
Even if there is a peak of the residual characteristic of the mechanical filter 3, such as 21 in Fig. 7a, the trigger level is still sufficiently maintained as 20 in Fig. 7a, so the Schmitt trigger circuit 6
The output of is not inverted. When the capacitor C of the peak hold circuit 15 completes discharging, the trigger level becomes the reference flea pressure and returns to the state 19. In this way, the output time is L in Figure 7b for the input time of the control signal, that is, T in Figure 7a, and even if the input level becomes excessive, the output time will not be extended as shown in Figure 3b. Without it, there is almost no change.

以上説明したように、メカニカルフィル夕を使ってある
制御信号を検出しようとするとき、本発明の回路によっ
て制御信号のレベルに応じて自動的にトリガレベルが選
ばれるため、レベルマージンを拡大することができるだ
けでなく、たとえメカニカルフィル夕の特性にばらつき
があってもそれを吸収するように動作するので従来のよ
うに回路の調整の必要がない。
As explained above, when trying to detect a certain control signal using a mechanical filter, the trigger level is automatically selected according to the level of the control signal by the circuit of the present invention, so the level margin can be expanded. Not only that, but even if there are variations in the characteristics of the mechanical filter, it operates to absorb them, so there is no need to adjust the circuit as in the case of conventional filters.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従釆の制御信号受信回路のブロック図、第2図
、第3図および第4図は第1図の説明に供する波形図、
第5図は本発明の制御信号受信回路のブロック図、第6
図は本発明要部の結線図、第7図は本発明の説明に供す
る波形図である。 2,4……増幅器、3……メカニカルフィル夕、5・・
・・・・整流回路、6・・・・・・シュミットトリガ回
路、15・・・・・・ピークホールド回路、16・・・
・・・ダイオードスイッチ回路。 第1図 第2図 第3図 第4図 第5図 第6図 第7図
FIG. 1 is a block diagram of a subordinate control signal receiving circuit; FIGS. 2, 3, and 4 are waveform diagrams for explaining FIG. 1;
FIG. 5 is a block diagram of the control signal receiving circuit of the present invention, and FIG.
The figure is a wiring diagram of essential parts of the present invention, and FIG. 7 is a waveform diagram for explaining the present invention. 2, 4...Amplifier, 3...Mechanical filter, 5...
... Rectifier circuit, 6 ... Schmitt trigger circuit, 15 ... Peak hold circuit, 16 ...
...Diode switch circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

【特許請求の範囲】[Claims] 1 受信した制御信号を増幅する増幅器と、受信する制
御信号の周波数にのみ感応するメカニカルフイルタと、
該メカニカルフイルタからの出力信号を増幅する増幅器
と、該増幅器からの交流電圧を直流電圧に変換する整流
回路と、該整流回路からの直流電圧を波形整形するシユ
ミツトトリガ回路から成る制御信号受信回路において、
前記整流回路により得られた直流電圧を分圧して得られ
たピーク電圧を一定時間だけ保持するピークホールド回
路と、該ピークホールド回路により得られた電圧と、基
準電圧とを比較して大きい方の電圧をトリガレベルとし
て出力するスイツチ回路とを備え、該スイツチ回路によ
り得られたトリガレベルと、前記整流回路からの電圧と
により前記シユミツトトリガ回路を駆動するようにした
ことを特徴とする制御信号受信回路。
1. An amplifier that amplifies the received control signal, a mechanical filter that is sensitive only to the frequency of the received control signal,
A control signal receiving circuit comprising an amplifier that amplifies the output signal from the mechanical filter, a rectifier circuit that converts the AC voltage from the amplifier into a DC voltage, and a Schmitt trigger circuit that shapes the waveform of the DC voltage from the rectifier circuit,
A peak hold circuit that holds the peak voltage obtained by dividing the DC voltage obtained by the rectifier circuit for a certain period of time, and compares the voltage obtained by the peak hold circuit with a reference voltage and selects the larger one. A control signal receiving circuit comprising: a switch circuit that outputs a voltage as a trigger level; and the Schmitt trigger circuit is driven by the trigger level obtained by the switch circuit and the voltage from the rectifier circuit. .
JP14500479A 1979-11-09 1979-11-09 Control signal receiving circuit Expired JPS6013629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14500479A JPS6013629B2 (en) 1979-11-09 1979-11-09 Control signal receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14500479A JPS6013629B2 (en) 1979-11-09 1979-11-09 Control signal receiving circuit

Publications (2)

Publication Number Publication Date
JPS5668045A JPS5668045A (en) 1981-06-08
JPS6013629B2 true JPS6013629B2 (en) 1985-04-08

Family

ID=15375218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14500479A Expired JPS6013629B2 (en) 1979-11-09 1979-11-09 Control signal receiving circuit

Country Status (1)

Country Link
JP (1) JPS6013629B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180070164A (en) * 2016-12-16 2018-06-26 엘지이노텍 주식회사 Electronic shelf label, lighting apparatus, and controlling apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5884528A (en) * 1981-11-16 1983-05-20 Noboru Yamaguchi Digital signal wave shaping circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180070164A (en) * 2016-12-16 2018-06-26 엘지이노텍 주식회사 Electronic shelf label, lighting apparatus, and controlling apparatus

Also Published As

Publication number Publication date
JPS5668045A (en) 1981-06-08

Similar Documents

Publication Publication Date Title
US4943712A (en) Motion detector
US4173739A (en) Overload detecting circuit for a PWM amplifier
GB2073977A (en) Gain control circuits
US4481553A (en) Protection circuit
US4509022A (en) Amplifier circuit with automatic gain control and hearing aid equipped with such a circuit
JPS6013629B2 (en) Control signal receiving circuit
US3748496A (en) Sound activated controller
US4287513A (en) Door knob alarm device
JPH054334Y2 (en)
JPS6127714B2 (en)
US4527121A (en) Short-circuit-protected evaluation circuit of high stability for variable inductance transducers
US4890265A (en) Infra-sonic detector and alarm with self adjusting reference
CN223664932U (en) Intelligent conference room control system
JP2516002Y2 (en) Smoke detectors
JPS5824048B2 (en) directional pulse transmitter
JPS6210593Y2 (en)
JPS6319913Y2 (en)
JPH0431675Y2 (en)
JP3074782B2 (en) Human body detector
CZ5616U1 (en) Circuit arrangement of electronic unit for assessment of change in sensor capacitance
JPH0334025B2 (en)
JPH0128451Y2 (en)
JPS6317363B2 (en)
JPH0514096A (en) Photoelectric sensor light receiving amplifier circuit
JPH0252970B2 (en)