JPH0334085B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a process signal input/output device for a programmable controller.

[Conventional technology]

There was a conventional process signal input/output device as shown in Figure 2 (Mitsubishi Electric MELPLAC).
-550 Instruction Manual 3 “Process Input/Output” published in 1982). In the figure, 1 is a CPU (central processing unit), 2 is a process signal input/output device, 3 is a bus buffer device, 4 is an input/output signal interface device, 5 is a CPU side input/output bus, and 6 is a process side input/output bus. , 7 is a bus driver/receiver, 8 is a parity checker, 9 is an input/output address signal, 10
is an input/output data signal, 11 is a bus control signal, 12 is
are control objects (hereinafter referred to as processes) such as an operation panel and a solenoid valve (not shown).

Next, the operation will be explained. The CPU 1 and the process 12 are electrically connected via a bus buffer device 3 and an input/output signal interface device 4 housed in a process signal input/output device 2, and signals are transmitted. A plurality of process signal input/output devices 2 are usually provided, and are connected to the CPU 1 via an input/output bus 5. The bus buffer device 3 and the input/output interface device 4 are connected by a process input/output bus 6, and the input/output interface device 4 is connected to the process 12 by a cable. A unique address is set in advance in the input/output interface device 4, and the CPU 1 uses the address to specify the process 12 to which information is to be transmitted.
The configurations of the input/output buses 5 and 6 are the same, and include an input/output address signal 9, an input/output data signal 10, and
A bus control signal 11 for communication between the CPU 1 and the input/output interface device 4 is included. A parity bit is usually added to the input/output address signal 9 and the input/output data signal 10, and the CPU
1. Error checking is performed in each part of the bus buffer device 3 and input/output signal interface device 4. The bus buffer device 3 is a bus driver/
It is composed of a receiver 7, a parity checker 8, etc., and performs bus signal amplification, impedance matching, timing matching, and parity checking.

[Problem that the invention seeks to solve]

Conventional process signal input/output devices are configured as described above, so the process side input/output bus and
The CPU side input/output bus must be the same, the address width must be the same, and the failure detection method must be the same, which increases the hardware scale for failure detection or increases the CPU load (access frequency). However, there was a problem in that when a failure occurred, the location that caused it was unclear.

This invention was made to solve the above problems, and it reduces the bus width of the process side input/output bus, simplifies the circuit configuration of the input/output interface device, and reduces the bus access frequency of the CPU. It is an object of the present invention to provide an inexpensive and highly reliable process signal input/output device that can improve failure detection ability without increasing performance.

[Means for solving problems]

The process signal input/output device according to the present invention includes:
An address translation device that converts the width of the address output from the CPU, a parity checker/generator that performs a parity check of data output from the CPU, and a parity checker/generator that performs a parity check on the data output from the CPU, and an input/output signal interface device that handles read and write data and converts this data. It is equipped with an input/output bus management device consisting of an inversion double-transmission verification device that checks inversion data.

[Effect]

In the input/output bus management device of the present invention, the width of address data is reduced by the address conversion device, and parity checks can be performed in common by having a common parity checker/generator.
Reliability is improved because reading and writing are sufficiently checked by the reversing double-feed collation device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, 1 is a CPU, 2 is a process signal input/output device, 3A is an input/output bus management device, 4 is a
is an input/output signal interface device, 5 is a CPU side input/output bus, 6 is a process side input/output bus, 7 is a bus driver/receiver, 8 is a parity checker,
9a, 9b are input/output address signals, 10a, 10
b is an input/output data signal, 11a, 11b are bus control signals, 12 is a process, 13 is an input/output address conversion device, 14 is a parity checker/generator, 15 is an inversion double-transmission collation device, and 16 is a timing control device.

Next, the operation will be explained. First, the CPU 1 and the input/output bus management device 3A are connected by a CPU side input/output bus 5, and this input/output bus 5 includes an input/output address signal 9a, an input/output data signal 10a,
A bus control signal 11a is included. here,
Each input/output address signal 9a and input/output data signal 10a between the CPU 1 and the input/output bus management device 3A
A pie data bit is added to the data, and is checked on each receiving side. That is, the input/output address signal 9a is checked by the parity checker 8, and the parity check of the CPU output data and the parity generation of the CPU input data are performed by the parity checker/generator 14.

The CPU 1 is connected to an input/output bus management device 3A via a CPU-side input/output bus 5, and input/output address signals 9a and input/output data signals 10a are relayed with parity bits added, and bus control signals 11a is also relayed. These signals are checked on the receiving side, and among these, the input/output address signal 9a is checked by the parity checker 8, and
A parity checker/generator 14 performs a parity check on data output from the CPU and a parity generation input to the CPU.

In the process signal input/output device configured as described above, when the CPU 1 attempts to access, for example, one of the four input/output signal interface devices 4 shown in FIG. The common address and individual addresses of the four input/output signal interface devices 4 within the management range are specified to the management device 3A. When the input/output address conversion device 13 receives this designation and recognizes that the common address is the address of its own device, it converts only the individual addresses excluding the common address to the input/output signal interface via the process side input/output bus 6. Output to device 4.

As a result, the width of address data (the number of address constituent bits) is reduced in the process of converting from the CPU side input/output address 9a to the process side input/output address 9b.

Next, the input/output bus management device 3A and the input/output interface device 4 are connected via a process side input/output bus 6, and the input/output data signal 1 between them is connected.
The check for 0b is performed by the reversal double feed collation device 15. That is, when the CPU 1 reads data from the input/output interface device 4, the input/output interface device 4 reads data from the timing control device 16.
The input/output data 10b is transmitted twice at the timing based on the bus control signal 11b modified by the bus control signal 11b. The data sent out for the second time is the inverted signal data of the data sent out the first time, and these two data are checked by the inversion double-transmission verification device 15 to see if they match. On the other hand, when the CPU 1 writes data to the input/output interface device 4, the input/output interface device 4 outputs the bus control signal 11b.
At a timing based on , the inversion of the written data is sent to the input/output bus management device 3A.
Then, the data is checked by the reversal double-transmission collation device 15 in the same way as when reading the data.

In the above embodiment, the bus configuration is such that the address and data signal lines are separate, but a configuration in which the addresses and data are switched and shared in chronological order is very good. A similar effect can be achieved even in the case of a bus having separate signal lines for input and output.

〔Effect of the invention〕

As described above, according to the present invention, the address data from the CPU is divided and converted into only the address data necessary for the input/output signal interface, and the address data between the CPU and the input/output signal interface device is divided. Since data is read or written within the process signal input/output device, the bus width of the process-side input/output bus can be reduced, and the parity checker/generator, which was conventionally included in each input/output interface device, can be replaced with the input/output bus. It can be shared in the management device, making the hardware smaller and reducing production costs.
In addition, reliability can be improved, and furthermore, by separating and reducing the failure monitoring area, maintainability can also be improved, and other excellent effects can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional process input/output device. In the figure, 1 is a CPU, 3A is an input/output bus management device, 4 is an input/output interface device, and 5 is an input/output interface device.
CPU side input/output bus, 6 is process side input/output bus,
12 is a process (controlled object), 13 is an input/output address conversion device, 14 is a parity checker/generator, and 15 is an automatic double-transmission verification device. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Controlled by the CPU via the CPU side input/output bus, and in response to this control, information is transmitted to the controlled object by multiple input/output interface devices internally connected via the process side input/output bus. In the process signal input/output device of a programmable controller that performs an address conversion device that divides address data, reduces the address width to only necessary address data, and outputs the reduced address width to the input/output signal interface device via the process side input/output bus; a parity checker/generator that performs parity check and parity generation for the CPU; and a parity checker/generator that performs parity generation for the CPU;
Alternatively, the present invention is characterized by comprising an inversion double-transmission verification device that checks data whose timing is controlled by a timing control device written from the CPU to the input/output signal interface device and data obtained by inverting these data. Process signal input/output device.