JPH0334246B2 - - Google Patents

Description

[Detailed description of the invention] TECHNICAL FIELD The present invention relates to digital signal equipment.

Differential filtering and smoothing operations on digital signals are one of the basic calculation processes in fields such as automatic waveform measurement and digital image processing.
Generally, when performing digital filtering processing on discrete time-series signals, multiplication/division processing is required. Conventionally, when this process is implemented using software using a minicomputer or a microcomputer, there is a drawback that the repeated operations of multiplication and division take time and are difficult to apply to real-time processing of signals. On the other hand, if the above filtering processing is to be implemented in hardware, a multiplication/division circuit is required, resulting in a complex circuit configuration, the calculation speed being affected by the data length, and the need for high accuracy. There was a problem.

Furthermore, conventionally, differential filtering and smoothing operations on time-series signals are performed using filters with different configurations, so if the original time-series signal at the same time is input to different filters, the output The signals have a phase shift, making it difficult to synchronize each filtering output signal or with the original signal.

An object of the present invention is to provide a signal processing device that can appropriately select different types of filtering processing such as high-order differential filtering and smoothing, and can also obtain these output signals at the same time without phase shift. That's true.

According to the present invention, an input digital signal sampled in time series is delayed, and a pair of second and third signals, which are equally spaced before and after the first signal, are predetermined as a pair. delay means for outputting a number of pairs of signals; a first delay means for multiplying the first signal by a first coefficient signal having a value of 0 or 1;
a multiplier of +1 or -1; and the second signal;
a second multiplication means for multiplying the third signal by a second coefficient signal having a value of , a first addition means for adding the third signal and the output of the second multiplication means;
The basic circuit has a third multiplication means for multiplying the output of the addition means by a second coefficient signal that takes a value of 0 or 1 corresponding to the time interval of the second or third signal. In addition to providing a predetermined number of
a first adding means, each including a second adding means for adding the outputs of these basic circuits, and a third adding means for adding the output of the first multiplication means and the output of the second adding means; second and third filter circuits, the second filter circuit being the first filter circuit;
The first signal of the filter circuit is input as the input digital signal, and the third filter circuit is configured by inputting the output of the third adding means of the first filter circuit as the input digital signal. a signal processing device which delays an input digital signal sampled in time series and generates second and third signals at equal intervals before and after the first signal; a delay means for outputting a predetermined number of pairs of signals as a pair; a first multiplication means for multiplying the first signal by a first coefficient signal having a value of 0 or 1; a second multiplier that multiplies the second signal by a second coefficient signal that takes a value of +1 or -1; and a first multiplier that adds the third signal and the output of the second multiplier. and a third multiplication that multiplies the output of the first addition means by a second coefficient signal that takes a value of 0 or 1 corresponding to the time interval of the second or third signal. a predetermined number of basic circuits having means; and a second addition means for adding the outputs of these basic circuits, and an output of the first multiplication means and an output of the second addition means. first and second filter circuits each having a third addition means for adding, and the second filter circuit includes an output of the third addition means of the first filter circuit of the filter circuit. There is obtained a signal processing device characterized in that it is configured by inputting the above-mentioned input digital signal as the input digital signal.

Next, the present invention will be explained in detail. The ideal frequency characteristic in low-frequency differential processing is given by equation (1).

H〓 ⁽¹⁾ (ω)=jω |ω|≦απ 0 απ<|ω|<π (1) Here, απ (0<α<1) indicates the cutoff frequency, and the sampling period is assumed to be T=1. are doing.

This frequency characteristic is shown in FIG. When the characteristic expressed by equation (1) is approximated by an acyclic symmetric FIR filter, its frequency characteristic is given by equation (2).

F ⁽¹⁾ (ω)=j _P 〓 ⁿ⁼¹ _o sin nω (2) Expressing equation (2) in the time domain, the output signal sequence y _k ⁽¹⁾ of first-order differential filtering is expressed as equation (3). It is expressed as the waveform sum of central differences of the input signal sequence x _k as shown in FIG.

y _k ⁽¹⁾ = d/2 _P 〓 ⁿ⁼¹ h _o (x _k+o −x _ko ) (3) Here, h _o = d・_ho , d=1/ _P 〓 ⁿ⁼¹ (n・h _o )T
shows. In equation (3), d is a scale factor (constant) and is unrelated to the difference calculation in equation (3), so there is no need to take it into account in actual calculation. Furthermore, in equation (3), if _ho is set to "0" or "1", equation (3) shows that the first-order differential characteristic can be realized by only difference calculation.

Next, the frequency characteristics in the smoothing process are expressed by equation (4).

F ^(m) (ω)= ₀ ^(m) +2 _P 〓 ⁿ⁼¹ _o cos(nω) (4) Expressing equation (4) in the time domain, the smoothed processing output signal
y _k ^(m) is expressed as a linear sum of the input signal sequence x _k and a temporally symmetric signal sequence centered on x _k , as shown in equation (5).

y _k ^(m) = h ₀ ^(m) x _k + _P 〓 ⁿ⁼¹ h _o ^(m) (x _k+o + x _ko ) (5) where _o ^(m) = d・h _o ^(m) , d=1/ _P 〓 ^n=-P h _o ^(m) . In equation (4), d is a scale factor (constant), and if h _o ^(m) is “0” or “1”, equation (5) shows that smoothness can be achieved with only a simple linear sum. It shows.

Now, if we pay attention to the difference term (x _k+o −x _ko ) in equation (3), the linear sum term (x _k+o + x _ko ) in equation (5) can be expressed as
This corresponds to the sign of the time series signal x _ko in the second term in (3) converted. This shows that the smoothing operation based on equation (5) is achieved by replacing the subtraction operation with an addition operation among the differential operations expressed in equation (3), and adding the term corresponding to h ₀ . There is. FIG. 2 shows a system in which the selection between the subtraction operation and the addition operation can be switched and selected using an external signal. By connecting an addition device and a signal delay device to the arithmetic system shown in FIG. 2, a signal processing device that can be used in conjunction with the differentiation and smoothing processing shown in equations (3) and (5) can be realized.

The signal processing method of the present invention is generally expressed by equation (6) using equations (3) and (5).

y _k = h ₀ x _k + _P 〓 ⁿ⁼¹ h _o (x _k+o + j・x _ko ) (6) Here, h _o h ₀ =0 or 1 and j=±1. Equation (6) is realized as a processor as shown in FIG. 3, in which the signal delay means and the addition means include addition/subtraction selection means. In Figure 3, 1 is the maximum of 2p+1
2 corresponds to a means for calculating coefficients such as h ₀ and _ho in equation (6) and performing a linear sum or difference calculation. In the configuration shown in FIG. 3, by appropriately selecting the clock and setting coefficients such as h ₀ to _ho , j, etc. according to the desired filtering operation, the time ( p
A differential filtering output (or smoothed output) y _k of the original signal x _k at times separated by +1) is obtained. Here, y _k is synchronized with the original signal x _k ,
There is no phase shift.

Next, the processor that performs the operations shown above is shown in Figure 4.
Connect them in cascade to create a tree structure. The above processor is denoted by F, and the i-th processor in hierarchy J is denoted by F ^(J) _i . As described above, by inputting a time series signal to F ^(J) _i , a thickness signal delayed by time p+1 from the input signal is generated.
x ^(J) _i , ₁ and its filtered output signal x ^(J) _i , ₂ are obtained. Next, the output signal of F ^(J) _i is processed by a processor F ^(J+1) _i which has differentiation or smoothing characteristics in the next stage.
F ^(J+1) Input to _i+1 . Processor F ^(J+1) _i , F ^(J+1) _i+
1 outputs four types of signals x ^(J+1) _i , ₁ and x ^(J+1) _i , ₂ and
As shown in the above explanation, x ^(J+1) _i+1 , ₁ and x ^(J+1) _i+1 , ₂ have no phase shift. Also, the signal x ^(J+1) _i , ₁ and
x ^(J+1) _i+1 , ₁ , x ^(J+1) _i , ₂ , x ^(J+1) _i+1 , ₂ also F ^(
J+1) _i F (J+ ₁ ⁾ Since there is no phase shift in the input signals x ^(J) _i-1 , x ^(J) _i , and ₂ to i+1, they are assumed to have occurred at the same time. be able to. Therefore, by cascading such processors to create a tree structure, all the various filtering output signals on the same layer of the tree will be in phase, and each signal will be It shows the results of different filtering processes.

Further, as explained above, the processor shown in FIG. 3 performs differential filter linking operations or smoothing operations with a variety of different frequency characteristics by selecting addition/subtraction and changing coefficients using external signals. Therefore, when these processors are connected in multiple layers in the structure shown in Fig. 4, depending on the characteristics of each processor, the multi-stage (high-order) differential filtering output signal, the high-order smoothing output signal, and the high-order smoothing of the high-order differential output signal. The output signals are the same and can be obtained from a simple configuration.

Next, an embodiment of signal processing in which the aforementioned processors are cascaded in three stages in a tree structure will be described. In FIG. 5, F ₁ and F ₃ operate as filters with differential characteristics, and F ₂ operates as a filter with smoothing characteristics. Regarding the operation, the first-order differential signal X' of the input signal X is obtained by the processor of _F1 . This differentiated signal X' is delayed by (p+1) clocks from the actual input signal and has the same phase as the other output signal X' of the processor. Next, F ₂ 's processor executes
A signal ″ is obtained by smoothing the signal X′, and this ″
is in phase with the signal X'' which is delayed by (p+1) blocks from X _' .
A signal obtained by _firstly differentiating the _output signal The signal X〓″ is obtained. In other words, in the lowest layer of this tree-structured signal processing system, a smoothed signal of the signal X'' delayed by 2 (p+1) clocks from the input signal ¨'' is obtained, and no phase shift occurs between these four types of signals.

Next, it will be shown below that by changing _ho in equation (6), the frequency characteristics change while having the same configuration. For example, if p in equation (6) is 4 and the processor shown in FIG. 3 is a processor that performs differential filtering (h ₀ = 0, j = -
1) 15 types of differential characteristics can be obtained by combining h ₁ , h ₂ , h ₃ , and h ₄ to “0” and “1”, respectively. Also, assuming that the processor shown in FIG. 3 is a processor that performs smoothing (j=+1), h ₀ , h ₁ , h ₂ , h ₃ ,
Thirty types of smoothing characteristics can be obtained by setting _h4 to "0" and "1", respectively. (At this time, all “0”
, and the case where only h ₀ is “1” have no meaning, so these are excluded. ) Therefore, if a processor is constructed with a multi-layered tree structure as shown in FIG. 5, a wide variety of filtering outputs will be obtained.
To give an example, in FIG. 5, the parameters of the processor F ₁ that performs differential filtering in the first layer are h ₀
=0, _h1 =0, _h2 =1, _h3 =1, _h4 =0, j=-
1, and the parameters of processor F ₃ that performs second-layer differential filtering are h ₀ = 0, h ₁ = 1, h ₂ =
1, _h3 =1, _h4 =0, and j=-1, the frequency characteristics of the second layer output signal, that is, the second-order differential output signal, are as shown in FIG.

Similarly, FIG. 7 is a diagram showing two-stage smoothing characteristics,
The parameters of the first stage are h ₀ = 1, h ₁ = 1, h ₂ = 1,
h ₃ = 0, h ₄ = 0, and j = 1, and the parameters in the second stage are h ₀ = 1, h ₁ = 1, h ₂ = 1, h ₃ = 1, h ₄
=0, and j=1.

Below, Figure 8 shows the differential and smoothing characteristics, and in the first stage
h ₀ = 0, h ₁ = 1, h ₂ = 1, h ₃ = 1, h ₄ = 0, j =
-1, in the second row h ₀ = 1, h ₁ = 1, h ₂ = 1, h ₃ =
0, h ₄ = 0, j = 1, and Figure 9 also shows differential/smoothing characteristics, and in the first stage, h ₀ = 0, h ₁ = 1, h ₂ = 0, h ₃
= 0, h ₄ = 0, j = -1, h ₀ ni 1 in the second stage, h ₁ =
0, h ₂ =0, h ₃ =0, h ₄ =1, and j=1.

As described above, according to the present invention, the following effects can be obtained compared to the conventional system. (1) Compared to known digital filters, this method does not require multiplication/division calculation processing, so high-speed processing is possible even in high-order filtering processing. (2) By configuring a processor that can perform both differential filtering and smoothing in a tree structure, a differential filtering output signal and a smoothed signal with no phase shift can be obtained at the final stage. (3) By changing the coefficients assigned to the tree-structured processors, it is possible to perform differential filtering or smoothing with a wide variety of frequency characteristics without changing the structure. . (4) Even when increasing the data length, the calculation speed and phase are not affected by the data length. (5) This method can be realized with a relatively simple configuration such as an adding means and a signal delaying means, and since the configuration is simply cascaded to form a multi-layered tree structure, the overall circuit configuration is simple. The number of components is also reduced compared to when a conventional digital filter is implemented using hardware.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing ideal frequency characteristics in low-frequency differential processing, FIG. 2 is a diagram showing an example of a configuration in which addition and subtraction operations are switched by an external control signal, and FIG. 3 is a diagram of the processor used in the present invention. FIG. 4 is a diagram showing an embodiment of the present invention, in which the configuration of FIG. 3 is configured into a tree structure, FIG. 5 is a diagram showing a specific example of the configuration of FIG. 3, and FIGS. 9 is a diagram showing an example of characteristics when a certain value of the parameter is selected.

Claims (1)

[Scope of Claims] 1: includes a first, second, and third filter circuit; each of the first, second, and third filter circuits delays an input digital signal sampled in time series; Then, the second signal (χ _ko ) and the third signal (χ _{k +o} ), which are equally spaced before and after the first signal (χ k ), are paired as a predetermined number ( P); and a first multiplication process (χ _k h 0 ) that multiplies the first signal by a first coefficient signal (h ₀ ) taking a value of 0 or 1 _. ), the second signal and +1 or -1
a second multiplication process (j·χ _ko ) that multiplies a second coefficient signal (j) having a value of , and a first process that adds the third signal and the multiplication result of the second multiplication process. (χ _k+o +j・χ _ko ), and a third signal that takes a value of 0 or 1 corresponding to the time interval between the addition result of the first addition process and the second or third signal. A third multiplication process ( _{ho ・}
(χ _k+o +j・χ _ko )) and a second addition process ( _P 〓 ⁿ⁼¹ h _o・(χ _k+o +j・χ _ko ))
and a third addition process (h ₀ ·χ _k + _P 〓 ⁿ⁼¹ h ₀ ·(χ _k+o +j·χ _ko )); the delay means of the second filter circuit inputs the first signal of the first filter circuit as the input digital signal; 3. A signal processing device, wherein the delay means of the third filter circuit inputs and outputs the addition result of the third addition process of the first filter circuit as the input digital signal. 2 comprising first and second filter circuits; each of the first and second filter circuits delaying a time-sequentially sampled input digital signal to center the first signal (χ _k ); a delay means for outputting a predetermined number (P) of paired signals of a second signal (χ _ko ) and a third signal (χ _k+o ), which are equally spaced back and forth in time series, as a pair; , a first multiplication process (χ k·h 0 ) that multiplies the first signal by a first coefficient signal (h ₀ ) that takes a value of 0 or 1, and a first multiplication process (χ _k ·h _{0 ) that multiplies the first signal by a first coefficient signal (h 0} ) that takes a value of 0 or 1; 1
a second multiplication process (j·χ _ko ) that multiplies a second coefficient signal (j) having a value of , and a first process that adds the third signal and the multiplication result of the second multiplication process. (χ _k+o +j・χ _ko ), and a third signal that takes a value of 0 or 1 corresponding to the time interval between the addition result of the first addition process and the second or third signal. A third multiplication process ( _{ho ・}
(χ _k+o +j・χ _ko )) and a second addition process ( _P 〓 ⁿ⁼¹ h _o・(χ _k+o +j・χ _ko ))
and a third addition process (h ₀ ·χ _k + _P 〓 ⁿ⁼¹ h ₀ ·(χ _k+o +j·χ _ko )); The delay means of the second filter circuit inputs the addition result of the third addition process of the first filter circuit as the input digital signal. A signal processing device characterized in that it is configured by