JPH043690B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a digital signal processing device.

Differentiation, smoothing, and filtering operations on digital signals have become one of the indispensable calculation processes in fields such as automatic waveform analysis and image processing. Generally, analog filters and digital filters are used as filters that perform differential operations and smoothing operations. Analog filters cannot change filter characteristics due to their structure, and only one characteristic can be obtained for one filter. On the other hand, if a digital filter is implemented using software, it is possible to create filters with various characteristics by changing the coefficients of the digital filter, but it is necessary to perform high-precision multiplication and division calculations, and many operations are required to execute the program. Real-time processing was difficult in terms of calculation speed because it required long cycles.

In addition, in digital filters realized by hardware, when it is desired to obtain multiple filtering outputs with different characteristics, filters with different characteristics are usually arranged and operated in parallel, but this makes the configuration complicated. Moreover, a phase shift occurred in the plurality of filtering outputs obtained. In addition, the coefficients that determine the characteristics of such filters require a large number of significant digits, which increases the processing time. It was difficult to operate the filter as a filter.

An object of the present invention is to provide a signal processing device that can select many types of differentiation or smoothing filtering operations during the sampling time of a time-series signal by speeding up the calculation time of one filtering operation. It is.

According to the present invention, a digital signal sampled in time series is delayed, and a second clock signal is generated at equal intervals before and after the first signal in response to a predetermined first clock centered on the first signal. and a third signal as a pair and outputting a predetermined number of pairs of signals, the first signal and a first coefficient signal having a value of 0 or 1 are compared with the first clock. a first multiplier that multiplies in response to a second clock having a short cycle; and a second coefficient signal that takes a value of +1 or -1 by the second second multiplication means for multiplying in response to;
a first addition means for adding the third signal and the output of the second multiplication means, corresponding to a time interval between the output of the first addition means and the second or third signal; A predetermined number of basic circuits each having a third multiplication means for multiplying by a second coefficient signal having a value of 0 or 1 are provided, and a second addition means for adding the outputs of these basic circuits. , and third addition means for adding the output of the first multiplication means and the output of the second addition means.

Next, the present invention will be explained in detail. The output signal sequence y ^(l) of the first-order differential filtering _is the input signal sequence
X is expressed as a linear sum of central differences of _k .

y ^(l) _k = d/2 _P 〓 ⁿ⁼¹ h _o (X _k+o −X _k+o ) (1) where d=1/ _P 〓 ⁿ⁼¹ (n・h _o )・T be.

In equation (1), d is a scale factor (constant)
Since it is unrelated to the difference calculation in equation (1), there is no need to consider it in the actual calculation. Furthermore, (1)
This shows that if _ho is set to "0" or "1" in the equation, equation (1) can be realized using first-order differential characteristics using only difference calculations. On the other hand, the smoothed output signal y ^(m) _k is expressed as a linear sum of the input signal series X _k and a temporally symmetric signal series centered on X _k , as shown in equation (2).

y ^(m) _k = h ^{(m) p} _{X k} + _P 〓 ⁿ⁼¹ _h ^{( m)} _o (X _{k+ o +} =1/ _P 〓 ⁿ⁼¹ h ^(m) _o In equation (2), d is the scale factor (constant)
, and if h ^(m) _o is “0” or “1”, then (2)
The formula shows that smooth characteristics can be achieved using only a simple linear sum.

Now, if we pay attention to the difference term (X _k+o −X _ko ) in equation (1), the linear sum term (X _k+o +X _{ko )} in equation (2) becomes (1)
This corresponds to converting the sign of the time series signal X _ko in the second term in the equation. Therefore, if equations (1) and (2) are expressed as a common equation, equation (3) is obtained.

^y _{k = h p _ _ _ _ _} Otherwise, it takes a value of "1". j is also a coefficient for determining the characteristics of the filter and takes a value of "1" to "-1". When equation (3) is treated as a differential characteristic, j=-1 and h _p =0. Further, in the case of smoothing characteristics, j=1 and h _p =1. The processor corresponding to equation (3) has the configuration shown in FIG.

In the processor shown in Figure 1, 1 is a maximum of 2p
It is a signal delay means with a delay time of +1, and 2 is
This corresponds to means for calculating coefficients such as h _p to h _p in equation (3) and performing linear sum or difference calculations. This processor adjusts the predetermined differentiation or smoothing characteristic to its output by changing the coefficients h _p ~ h _p , _j .
obtained in y _k . When this processor is operated in synchronization with the clock controlling the signal acquisition time, the data in the delay means 1 remains unchanged until the next clock acquires the signal relating to the next time.
Utilizing this time, if the coefficients of h _p to h _p and j are changed and given to this processor while taking timing with another short clock, different data can be obtained with respect to the same data that has been delayed by the delay means. A filtered output signal is obtained. In other words, various types of filtering are possible. This can be achieved because the calculation time of this processor consists only of the switching time of a simple configuration such as the addition means, and is shorter than the cycle of the signal acquisition time.

FIG. 2 shows a timing chart when four types of filtering characteristics are obtained. In FIG. 2, T ₅ is the time during which data is actually acquired by the clock, and T _D is the time during which calculations are performed when special numbers representing each characteristic are given. Also, the clock CL is a clock that controls the delay operation of the signal delay means, and the characteristic selection signal S _e is a clock that controls the delay operation of the signal delay means.
With shorter synchronization the coefficients h _p ~ h _p and j are a, b,
Change it to c, d. Accordingly, outputs A, B, C, and D for different filtering characteristics are obtained as outputs S _p .

Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention. In FIG. 3, A/D
The converter 3 samples the original analog signal at regular time intervals to generate a time-series digital signal sequence. The processor 4 corresponding to FIG. 1 performs a predetermined filtering process according to the given coefficients. Multiplexer 5 provides coefficients a through d for each filtering characteristic to the processor according to the timing of clock CL'. The multiplexer 6 distributes the filtered output processed by the processor 4 to the multiplexer 6 as different filtered output signals depending on the timing of the clock CL'.

Next, we will discuss the operation. The analog signal input to the A/D converter 3 is output as a digital signal sequence. This digital signal is subjected to differentiation or smoothing processing in the processor 4. At this time, the multiplexer 5 divides the digital signal into four signals at the timing of the characteristic selection clock CL' within the time until the next digital signal is input to the processor 4. species coefficient a
~d while switching. The filtering output signal from the processor 4 is sent to different filtering output signals A, B, C,
Sorting is done as D. Most of the timing deviation of the characteristic selection clock CL' for multiplexers 5 and 6 corresponds to the calculation speed of the processor, but the calculation speed of the processor is much faster than the A/D clock CL. Yes, there are almost no problems in terms of real-time processing.

FIG _. 4 is a _time chart for explaining the operation timing of the embodiment _shown in FIG _. In the figure, the phase delay t _S is due to the time delay due to A/D conversion and the shift register which is the delay means. Also, the phase delay _tD is due to the adder and logic.

5 to 8 are diagrams showing different filtering characteristics obtained by the present invention, and FIGS. 6 and 8 show differential characteristics, and the coefficient values at that time are (j=-1, h _p = 0, h ₁ = 1, h ₂ = 1, h ₃ =
1), (j = -1, h _p = 0, h ₁ = 0, h ₂ = 1, h ₃ =
1). Figures 5 and 7 are diagrams showing smoothing characteristics,
The coefficient values at that time are (j=-1, h _p =
1, h ₁ = 0, h ₂ = 1, h ₃ = 1), (j = 1, h _p =
1, h ₁ =0, h ₂ =0, h ₃ =1).

As described above, according to the present invention, the following effects can be obtained compared to the conventional system.

(1) By using a processor consisting of a signal delay means and an addition means, it is possible to obtain a plurality of filtering outputs within a gate time having a certain period without changing the configuration.

(2) Filtering outputs having a plurality of characteristics can be obtained from a digital input signal sequence simultaneously and almost in real time.

(3) The multiple filtered output signal sequences obtained by this method can be considered to have the same phase, and each output signal sequence can be analyzed as a whole when extracting features such as biological signal waveforms. This is effective when doing the following.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a processor that performs filtering processing according to the present invention, FIG. 2 is a diagram showing the timing when four types of filtering characteristics are obtained in the same configuration, and FIG. 3 is an embodiment of the present invention. 4 is a diagram showing the operation timing of the embodiment shown in FIG. 3, and FIGS. 5 to 8 are diagrams each showing examples of filtering characteristics obtained by the present invention.

Claims (1)

[Claims] 1. A digital signal sampled in time series is delayed, and the digital signal is sequentially sampled back and forth in time series in response to a predetermined first clock centered on the first signal (X _k ). a delay means for outputting a predetermined number (P) of pairs of signals, with a second signal (X _ko ) and a third signal (X _k+o ) having an interval of one pair; Alternatively, a first multiplication process _{(x k ·} h ₀ ), and a second multiplication process (j x _ko ) of multiplying the second signal and a second coefficient signal (j) having a value of +1 or -1 in response to the second clock. and a first addition process (X _k+o +j・X _ko ) that adds the third signal and the multiplication result of the second multiplication process; A third multiplication process ( _{ho ・}(X _k+o +j・X _ko )), and a second addition process ( _P 〓 ⁿ⁼¹ h _o・(X _k+o +
j・X _ko )) and a third addition process (h ₀ ·X _k + _P 〓 ⁿ⁼¹ h ₀・(X _k+o +j・
X _ko )))