JPH0334819B2 - - Google Patents

Description

Detailed Description of the Invention Field of the Invention The present invention involves pressing an indenter into a sample made of a metal material or the like to make an indentation on the sample, and from the indentation.
This invention relates to an indentation type hardness meter that measures the hardness of a sample.

BACKGROUND OF THE INVENTION Conventionally, such a push-in hardness tester scans and images an indentation made on a sample placed on a sample mounting stage using a scanning imaging device mounted on an imaging device mount. , a configuration has been proposed in which a hardness signal representing the hardness of the sample is obtained from the imaging output.

In the conventional push-in hardness tester having such a configuration, it is necessary to hold the sample mounting table and the imaging device mount at relative positions where the scanning and imaging device scans and images the indentation in a focused state.

However, the conventional indentation type hardness tester has the disadvantage that it requires the use of a complicated, large, and expensive device, and requires a relatively long time.

DISCLOSURE OF THE INVENTION Accordingly, the present invention seeks to propose a novel indentation type hardness tester that does not have the above-mentioned drawbacks.

According to the present invention, a focus signal representing the focal point at which the scanning imaging device scans and images the indentation is obtained from the imaging output of the scanning imaging device, and the focus signal is used to control the sample mounting table and the imaging device. The imaging device mounting body is moved to a relative position where the scanning imaging device scans and images the indentation in a focused state.

Therefore, the present invention does not have the above-mentioned conventional drawbacks.

Embodiment of the Invention FIGS. 1 and 2 show an example of the mechanical system of the indentation type hardness tester according to the invention, which has the configuration described below.

That is, it has a sample mounting table 1 that can be moved up and down.

This sample mounting table 1 is used to place a sample 2 on the sample 2 and press an indenter (not shown) into the sample 2, as shown in FIG. It is used to make a quadrangular pyramid-shaped indentation 3 as shown, and has the configuration described below.

That is, a cylindrical body 5 is fixedly disposed on a base 4, and a cylindrical body 6 having the above-described sample mounting table 1 attached to its free end is housed inside the cylindrical body 5 so as to be movable up and down. In this case, a racer screw 7 is attached to the inner peripheral surface of the cylindrical body 6 .

On the other hand, a screw shaft 9 is pivotally attached to the base 4, and is screwed into the main screw 7 of the cylinder body 6 described above, and has a gear 8 attached to its free end.

Further, a motor 10 is attached to the base 4, and its rotating shaft 11 is connected to the gear 12 attached to the base 4.
It is connected to the screw shaft 9 via a gear 13 pivotally connected to the screw shaft 9 and a gear 8 attached to the screw shaft 9 described above.

Therefore, when the motor 10 is driven to rotate in the forward direction, the screw shaft 9 rotates in the forward direction, and accordingly, the cylindrical body 6 rises, and therefore the sample mounting table 1 rises.

Further, if the motor 10 is rotated in the opposite direction, the screw shaft 9 is rotated in the opposite direction, and accordingly, the cylindrical body 6 is lowered, and therefore the sample mounting table 1 is lowered. ing.

Further, an example of the push-in hardness meter according to the present invention includes an imaging device mounting body 20.

The imaging device mounting body 20 includes a movable platen 22 on which a one-dimensional scanning imaging device 21 is mounted, and a holder 23 on which the movable platen 22 is movably mounted.

The holder 23 includes a cylindrical portion 24 and an annular portion 25 integrally extending outward in the radial direction from the upper end of the cylindrical portion 24.
, a cylindrical portion 26 extending upward integrally from the outer periphery of the ring portion 25, and a plate portion 27 integrally extending inwardly in the radial direction from the upper end of the cylindrical portion 26. and has. In this case, the cylindrical portion 24 has
A gear 28 is attached on its outer peripheral surface. Further, the plate portion 27 is provided with a slit 29.

Such a holder 23 has, in its cylindrical portion 24,
The upper end of a cylindrical body 41, which will be described later, is loosely inserted, and the lower end surface of the cylindrical part 24 is received by an annular plate 42 that extends outward in the radial direction from the outer periphery of the cylindrical body 41. freely rotatable around the cylindrical body 41 in the state,
It is arranged.

On the other hand, a support body 40 is fixedly provided on the base 4 described above, and a motor 30 is attached to the support body 40.

Further, the rotating shaft 31 of the motor 30 is connected to the holder 23 via a gear 32 attached thereto and a gear 28 attached to the cylindrical portion 24 of the holder 23 described above.

Therefore, when the motor 30 is rotated in the forward direction, the holder 23 is rotated in the forward direction, and when the motor 30 is rotated in the reverse direction, the holder 23 is rotated in the forward direction.
rotates in the opposite direction.

Furthermore, the above-mentioned movable platen 22 is arranged between the ring part 25 and the plate part 27 of the above-mentioned holder 23, along a line bb passing through the axis a of the holder 23 and orthogonal thereto.
It is arranged so that it can be moved freely.

Further, a rod 33 is attached to the upper part of the movable platen 22 integrally therewith.

This rod 33 is connected to the plate portion 27 of the holder 23 mentioned above.
It passes through a slit 29 provided in and extends upward and outward.

Moreover, the above-mentioned holder 23 is attached to the free end of the rod 33.
A racer screw 34 is provided which extends on a line parallel to line bb in a plane orthogonal to axis a of .

On the other hand, a motor 35 is mounted on the plate portion 27 of the above-mentioned holder 23, and a screw 37 is attached to the rotating shaft 36 of the motor 35, which engages with the main thread 34 provided on the above-mentioned rod 33.

Therefore, when the motor 35 is rotated in the forward direction, the movable platen 22 moves in the first direction along the line bb orthogonal to the axis a of the holder 23,
Moreover, if the motor 35 is driven to rotate in the opposite direction,
The movable platen 22 is aligned with a line b perpendicular to the axis a of the holder 23.
-b in a second direction opposite to the first direction.

Furthermore, the one-dimensional scanning imaging device 21 described above is
As is clear with reference to FIG. 5, a large number (2n+1) solid-state image sensors (photoelectric conversion elements)
En′, E _o-1 ′, ... E ₁ ′, E ₀ , E ₁ , E ₂ ... E _o are electrically connected in series and arranged one-dimensionally on a line. It has a configuration.

Such a one-dimensional scanning imaging device 21 has solid-state imaging devices E _o ′ to E ₁ ′,
E ₀ , E ₁ to _{E o} are arranged one-dimensionally on a line,
The arrangement line is provided so that it passes through the axis a of the holding body 23 and coincides with the line c-c perpendicular to the above-mentioned line b-b when viewed from the direction along the axis a of the holding body 23. .

Furthermore, an engagement pin 38 extending downward is installed in the ring portion 25 of the holder 23 described above.

On the other hand, switches 39 and 39' are mounted on the above-mentioned ring plate 42 and are operated by engagement with the engagement pin 38 set up on the above-mentioned holder 23. These, switches 39 and 3
9' maintains an interval of 90° when viewed from the axis a of the holder 23.

Furthermore, a support body 40 is provided on the base 4, and the above-mentioned cylinder body 41 is attached to it.

This cylindrical body 41 is attached to the support 40 so that its axis d extends in the up-and-down direction of the sample mounting table 1 mentioned above, and so that one end faces the sample mounting table 1.
installed on.

Further, an annular plate 42 is attached to the cylindrical body 41 and integrally extends outward in the radial direction.

Thus, the cylindrical body 41 and the ring plate 42 loosely insert the holder 23 into the cylindrical part 24 thereof, and the lower end surface of the cylindrical part 24 of the holder 23 is received by the ring plate 42. It is mounted so that it can rotate freely.

Therefore, the axis a of the holding body 23 mentioned above is aligned with the cylindrical body 4.
It coincides with the axis d of 1.

Further, a cylinder 43 is attached to the cylinder 41 from the side and is in communication with the cylinder 41, and a light source 44 is disposed within the cylinder 43.

However, the light from the light source 44 is directed onto the sample mounting table 1 through a lens 45 provided in the cylinder 42, a half mirror 46 provided in the cylinder 41, and a lens 47 provided in the cylinder 41. The light is made incident on the mounted sample 2, and its reflected light is made incident on the one-dimensional scanning imaging device 21 via a lens 47 and a half mirror 46.

As described above, an example of the mechanical system of the indentation type hardness tester according to the present invention has been clarified.

Next, with reference to FIG. 5, an example of the electrical system of the indentation type hardness tester according to the present invention having the above-mentioned mechanical system will be described along with its operation.

As described above, the light from the light source 44 passes through the lens 45, the half mirror 46, and the lens 47, and
The reflected light enters the sample 2 and passes through the lens 47 and half mirror 46 to the one-dimensional scanning imaging device 2.
1, the sample was scanned and imaged one-dimensionally from the one-dimensional scanning imaging device 21.
An imaging output (generally referred to as S) is obtained.

In this case, the one-dimensional scanning imaging device 21 is driven and controlled by a clock pulse CP from a clock pulse generating circuit 50 as shown in FIG. 4B.

By the way, as mentioned above, the one-dimensional scanning imaging device 21 includes a large number of solid-state imaging devices E _o ′, E _o-1 ′ . . .
E ₁ ′, E ₀ , E ₁ , E ₂ ...E _o are electrically connected in series and arranged one-dimensionally on the above-mentioned line c-c. .

Therefore, the imaging output S is the solid-state imaging device E _o ′,
E _o-1 ′...E ₁ ', E ₀ , E ₁ , E ₂ ... _E
For each scan, in general, S _o ′, S _o-1 ′...S ₁ ′, S ₀ ,
S ₁ , S ₂ ... are obtained sequentially as S _o .

Now, the third mark attached to the sample 2 on the sample mounting table 1
The line extending including the diagonal line (this is defined as the first diagonal line) connecting opposing points PX and PX' of the indentation 3 shown in the figure on a plane including the surface of the sample 2 is defined as the first diagonal line. 4 As shown in Figure A, let LX ₀ be the line extending to include the diagonal line (this is the second diagonal line) connecting the other opposing points PY and PY′, and let it be LY ₀ . do. Furthermore, line LX ₀ and line LY ₀
Let the intersection point be 0.

Also, the line seen on the plane including the surface of sample 2
Parallel to LX ₀ , from line LX ₀ in a direction perpendicular to line LX ₀ , toward point PY,
1/2 of the width f, which is smaller than the length of the diagonal (these are NX and NY, respectively), that is, f/2)
As shown in FIG. 4A, a plurality of m lines extending successively at equal intervals e to a range having a width of , are defined as LX ₁ , LX ₂ , _. Furthermore, the line
Parallel to LX ₀ , extend from the line LX ₀ in the direction perpendicular to the line LX ₀ toward the line PY' side, taking equal intervals e in sequence to the range having the above-mentioned width f/2. Let the plurality of m lines in the figure be LX ₁ ′, LX ₂ ′, ...LX _n ′.

In addition, parallel to the line LY ₀ , extend from the line LY ₀ in a direction perpendicular to the line LY ₀ toward the point PX side, taking equal intervals e in order to the range with the above-mentioned width f/2. LY ₁ , LY ₂ ,...
Let LY _n . Further, in parallel with the line LY ₀ , from the line LY ₀ in a direction perpendicular to the line LY ₀ , toward the line PX' side, equally spaced e is sequentially taken from the line to the range having the above-mentioned width f/2. LY ₁ ′,
Let LY ₂ ′, ...LY _n ′.

As shown in FIG. 2, the holding body 23 on which the one-dimensional scanning imaging device 21 described above is mounted is connected to the engaging pin 38 provided thereon by the switch 39' provided on the ring plate 42 described above. In the state in which the solid-state imaging devices E _o ′ to _{E 1} ′, E ₀ , E ₁ to E _o of the one-dimensional scanning imaging device 21 are engaged with When viewed from the direction along the axis a of the rotary disk 21, that is, the axis d of the cylindrical body 41 mentioned above, it is parallel to the above-mentioned line LX ₀ on the sample 2 placed on the sample mounting table 1, and The outer position of the sample 2 is adjusted and placed on the sample mounting table 1 so that it approximately coincides with the line LX ₀ , and the position where the holder 23 is rotated (this is the first rotation (referred to as "position").

Further, the holder 23 and the sample mounting table 1 are arranged so that the one-dimensional imaging device 21 focuses on the indentation 3 of the sample 2.
It is assumed that the object is at a descending relative position (this is called the reference position) rather than a relative position (this is called the in-focus position) where one-dimensional scanning imaging is performed.

In such a case, the above-mentioned one-dimensional scanning imaging device 2
1, the outputs S _o ' to S ₁ ', S ₀ , and S ₁ to _{S o,} which constitute the imaging output S obtained for each scan, are obtained as shown in FIG. 4C.

That is, for example, the outputs S _o ′ to _{S o-2} ′ and the outputs S _o-2 to _{S o} are approximately at the same level, and the outputs S _o-3 ′ to _{S 1} ′, S ₀ ,
Although S ₁ to _{S o-3} take a smaller level than the outputs S _o ′ to _{S o-2} ′ and S _o-2 to _{S o} , the outputs among the outputs S _o-2 ′ to _{S 1} ′
The output S _o-2 ′ near the output S _o-2 ′ including S _o-2 ′,
S _o-3 ′, S _o-4 ′... take on smaller levels one after another,
Also, outputs including output S _o-2 among outputs S _o-2 to S ₁
Outputs S _{o- 2} , S _o-3 , S _o-4 . . . in the vicinity of S o-2 are obtained by taking successively smaller levels.

In this case, the reason why the outputs S _o ′ to _{S o-2} ′ and S _o-2 to _{S o} are at almost the same level is because they are the outputs S _o ′ to
S _o-2 ′ and S _o-2 ~ _{S o} are the above-mentioned lines LX ₀ of sample 2
The solid-state image sensor
This is because E _o ′ to _{E o-2} ′ and E _o-2 to _{E o} are the imaged outputs.

In addition, the outputs S _o-2 ′, S _o-3 ′, S _o-4 ′... take on smaller levels one after another, and the outputs S _o-2 , S _o-3 ,
The reason why S _o-4 ,... takes on successively smaller levels is that the outputs S _o-2 ′, S _o-3 ′S _o-4 ′... of the indentation 3,
The inclined area near the point PX′ along the line LX ₀ when viewed from above is captured by solid-state imaging devices E _o-2 ′, E _o-3 ′, E _o-4 ′...
... is the output of the image, and the output S _o-2 ,
S _o-3 , _o-4 ... is the line LX ₀ of the indentation 3 when viewed from above
This is because the solid-state imaging devices E _o-2 , E _o-3 , E _o-4 . . . output images of the inclined region near the point PX along the line.

Furthermore, as described above, the one-dimensional scanning imaging device 2
The sample mounting table is arranged so that the above-mentioned array line c-c of the solid-state imaging devices E _o ′ to E ₁ ′, E ₀ , E ₁ to E _o of No. 1 coincides with the above-mentioned line LX ₀ . Although the sample 2 is placed on the sample holder 1 and the holder 23 is in the first rotating position described above, it is assumed that the holder 23 and the sample mounting table 1 are in the focused position as described above. do.

Even in such a case, the above-mentioned one-dimensional scanning imaging device 2
1, the above-mentioned output obtained for each scan
S _o '˜S ₁ ', S ₀ , S ₁ -S _o are obtained in the same manner as described above in FIG. 4C.

However, in this case, the outputs S _o ′ ~ S ₁ ', S ₀ , S ₁ ~
As shown in FIG. 4D, S _o ' can be obtained at a higher level than when the relative positions of the holder 23 and the sample mounting table 1 are at the above-mentioned reference position.

In addition, the rate of change in which the above outputs S _o-2 ′, S _o-3 ′, S _o-4 ′ ... become smaller sequentially, and the outputs S _o-2 , S _o-3 , S _o-4 ...
As shown in FIG. 4D, the rate of change in which . It will be done.

From the one-dimensional scanning imaging device 21, for each scan,
The imaging output S obtained by sequentially arranging the outputs S _o ′ to S ₁ ′, S ₀ , and S ₁ to S _o described above is supplied to the arithmetic processing circuit 51 .

Now, from the one-dimensional scanning imaging device 21, outputs S _o ′ to _{S 1} ′, S ₀ , S ₁ to S _o obtained from the one-dimensional scanning imaging device 21 for each scan are sequentially obtained for u scanning times from a certain time t ₁ . _o ′〜
As shown in FIG. 6A, S ₁ ′, S ₀ , S ₁ to _{S o} are sequentially converted to the first output S _1o ′ to S ₁₁ ′, S ₁₀ , S ₁₁ to _{S 1o} ;
Second output S _2o ′ ~ S ₂₁ ′, S ₂₀ , S ₂₁ ~ _{S 2o} ;...
Let the u-th outputs be S _uo ′ to S _u1 ′, S _u0 , and S _u1 to _{S uo} .

At that time, the above-mentioned arithmetic processing circuit 51
From the second output S _1o ′ ~ S ₁₁ ′, S ₁₀ , S ₁₁ ~ _{S 1o} , △S _1o ′=S _1o ′−S _1(o-1) ′ △S _1(o-1) ′=S _{1 (o-1)} ′−S _1(o-2) ′ 〓 △S ₁₁ ′=S ₁₁ ′−S ₁₀ △S ₁₁ ＝S ₁₁ −S ₁₀ △S ₁₂ ＝S ₁₂ −S ₁₁ 〓 △S _1o ＝ Differential output △S _{1o ′} , △S 1 _(o-1) ′,……△ expressed as S 1o −S _1(o-1)
S ₁₁ ′, △S ₁₁ , △S ₁₂ ...△S _1o is obtained, and the maximum difference output among these difference outputs △S _1o ′ ~ △S ₁₁ ′, △S ₁₁ ~ △S _1o (this is _S1 ) is determined and stored, and a positive pulse _P1 is output as shown in FIG. 6B.

Further, the arithmetic processing circuit 51 next performs the above-mentioned second
From the second output S _2o ′ ~ S ₂₁ ′, S ₂₀ , S ₂₁ ~ _{S 2o} , △S _2o ′=S _2o ′−S _2(o-1) ′ △S _2(o-1) ′=S _{2 (o-1)} ′−S _2(o-2) ′ 〓 △S ₂₁ ′=S ₂₁ ′−S ₂₀ △S ₂₁ ＝S ₂₁ −S ₂₀ △S ₂₂ ＝S ₂₂ −S ₂₁ 〓 △S _2o ＝ Differential output △S _{2o ′} , △S _2(o-1) ′,……△ expressed as S 2o −S _2(o-1)
S ₂₁ ′, △S ₂₁ , S ₂₂ ...△S _2o is obtained, and the maximum difference output among these difference outputs △S _2o ′ ~ △S ₂₁ ′, △S ₂₁ ~ △S _2o (this is △S ₂ ) is determined and stored, and a positive pulse _P2 is output as shown in FIG. 6B.

Furthermore, the arithmetic processing circuit 51 is configured as follows.
Regarding the first output S _3o ′ ~ S ₃₁ ′, S ₃₀ , S ₃₁ ~ _{S 3o} , and the fourth output S _4o ′ ~ S ₄₁ ′, S ₄₀ , S ₄₁ ~ S _4o ...
Performing the same operation as described above, the u-th output
From S _uo ′〜S _u1 , S _u0 , S _u1 〜S _uo , △S _uo ′＝S _uo ′−S _u(o-1) ′ △S _u(o-1) ′＝S _{u(o-1 )} ′−S _u(o-2) ′ 〓 △S _u1 ′＝S _u1 ′−S _u0 △S _u1 ＝S _u1 −S u0 △S _u2 ＝S _u2 −S _u1 〓 △S _uo ＝S _{uo −S} Differential output △S _uo ′, △S _{u(o-1) ′,……△ expressed as u(o-1 )}
S _u1 ′, △S _u1 , △S _u2 ... △S _uo is obtained, and the maximum difference output among these difference outputs △S _uo ′ ~ △S _u1 ′, △S _u1 ~ △S _uo (this is S _u ) is determined and stored, and a positive pulse P _u is output as shown in FIG. 6B.

As described above, the positive polarity pulses P ₁ , P ₂ . _. .
supplied to

The motor 10 receives positive polarity pulses P ₁ , P ₂ ... P _u
is sequentially supplied, the step rotates in the forward direction.

For this reason, the above-mentioned sample mounting table 1 is raised by steps from the above-mentioned reference position.

In this case, the gear ratio between the gears 12 and 13, the gear ratio between the gears 13 and 8, The above-mentioned screw shaft 9
The pitches of the screws and the main screws 7 of the cylindrical body 6 are selected.

Further, after outputting the above-described positive polarity pulses P ₁ to _{P u} , the arithmetic processing circuit 51 sequentially outputs u negative polarity pulses P ₁ ′ to P _u ′ as shown in FIG. 6B. Output.

These negative polarity pulses P ₁ ' to P _u ' are supplied to the motor 10 via the motor drive circuit 52 described above.

The motor 10 receives negative polarity pulses P ₁ ′, P ₂ ′...
Each time P _u ' is supplied sequentially, it rotates in a step in the opposite direction.

Therefore, in response to this, the above-mentioned sample mounting table 1 is stepped down from the above-mentioned raised position, and thus the sample mounting table 1 returns to the above-mentioned reference position.

Further, the arithmetic processing circuit 51 outputs the maximum difference output ΔS 1 until it finishes sequentially outputting the negative polarity pulses P ₁ ′ to P _u ′ or after outputting the pulse P _{u ′} . , ΔS ₂ , . . . ΔS _u (this is assumed to be the r-th maximum difference output ΔSr among the maximum difference outputs) is determined.

However, after outputting the above-mentioned pulse P _u ′, r
positive polarity pulses P ₁ ″ to Pr″ are output.

These positive pulses P ₁ ″ to P _r ″ are supplied to the motor 10 via the motor drive circuit 52 .

Therefore, the motor 10 again rotates stepwise in the forward direction, and in response, the sample mounting table 1 rises in steps and maintains its raised position.

By the way, the maximum difference outputs △S ₁ , △S ₂ ,...
...The maximum difference output ΔS _r in ΔS _u is determined by the one-dimensional scanning imaging device 21 scanning and imaging the sample 2 in the in-focus state, as is clear from the above description in FIG. 4D. In the case, the outputs S _ro ′ to S _r1 ′, obtained at a high level from the one-dimensional scanning imaging device 21
It is obtained from S _r0 , _r1 ~ S _ro .

In addition, the maximum difference outputs △S ₁ , △S ₂ , ... △ mentioned above
As is clear from the above description in _{FIG .} When imaging, it is obtained from the output obtained from the one-dimensional scanning imaging device 21 at a low level.

Therefore, based on the pulses P ₁ ″ to P _r ″ described above, the position where the sample stage 1 has been raised as described above is such that the one-dimensional scanning imaging device 21 scans and images the sample 2 in a focused state. This is the in-focus position mentioned above.

Therefore, after the sample stage 1 maintains the focused position,
Imaging output S obtained from the one-dimensional scanning imaging device 21
is obtained at a high level.

In the above description, the holder 23 on which the one-dimensional scanning imaging device 21 is mounted is in the first rotational position, and the solid-state imaging device described above is
Although the arrangement line c-c of E _o ′ to _{E 1} ′, E ₀ , and E ₁ to _{E o} has been described as coinciding with the above-mentioned line LX ₀ on the sample 2, now the holder 23 is in the above-mentioned first rotational position, the arrangement line c-c of the solid-state image sensor E _o ′ to E ₁ ′, E ₀ , E ₁ to E _o is
Assume that it exactly coincides with the above-mentioned line LX _n ' on sample 2.

Note that while the holder 23 is in the above-described first rotational position, the solid-state image sensors E _o ′ to E ₁ ′, E ₀ ,
The relationship in which the arrangement line c-c of E ₁ to E _o exactly coincides with the above-mentioned line LX _n ' on sample 2 is that
After maintaining the focused position as described above, the arithmetic processing circuit 51 outputs m negative polarity pulses G11 to G.
1 _n and its m negative polarity pulses G1 ₁ ~
G1 _n is supplied to the above-mentioned motor 35 via the motor drive circuit 53, and the motor 3
5 in the forward direction, and accordingly, the movable plate 22 is rotated along the line b--b.
This can be obtained by sequentially moving steps along the direction orthogonal to the line LX _n ' mentioned above. In this case, the rotating shaft 3 of the motor 35
The pitches of the screw 37 attached to 6 and the main screw 34 of the rod 33 of the movable platen 22 may be selected so that the movable platen 22 sequentially moves step by step by the distance e described above.

Further, as just described, when the holding body 23 is in the first rotational position, the above-mentioned array line c-
When c exactly coincides with the above-mentioned line LX _n ′ on the sample 2, as mentioned above, the sample mounting table 1
From time t ₂ after maintaining the above-mentioned focal point position,
(2m+1) The above-mentioned output obtained sequentially over the course of the trip
As shown in FIG. 7A, S _o ′ to S ₁ ′, S ₀ , S ₁ to S _o are calculated as the first output QXL _no ′ to QXL _n1 ′ in the same manner as described above in FIG. 6A. , QXC _n0 ′, QXR _n1 ′〜
QXR _no ′; 2nd output QXL _(n-1)o ′～
QXL _(n-1)1 ′, QXC _(n-1)0 ′, QXR _(n-1)1 ′～
QXR _(n-1)o ′;……mth output QXL _1o ′～
QXL ₁₁ ′, QXC ₁₀ ′, QXR ₁₁ ~ QXR _1o ′;th (m+
1) Second output QXL _0o ~ QXL ₀₁ , QXC ₀₀ ,
QXR ₀₁ ~ QXR _0o ; (m+2)th output
QXL _1o ~ QXL ₁₁ , QXC ₁₀ , QXR ₁₁ ~ QXR _1o : (m+3)th output Q×L _2o ~ Q×L ₂₁ , Q×
C ₂₀ , Q×R ₂₁ ~Q×R _2o ;...(2m+1)th output QXL _no ~QXL _n1 ,QXC _n0 ,QXR _n1 ~
QXR _no .

At that time, the above-mentioned arithmetic processing circuit 51 outputs the above-mentioned first outputs QXL _no ′ to QXL _n1 ′,
Remember QXC _n0 ′, QXR _n1 ′ ~ QXR _no ′, and then △QXL _no ′=QXL _no ′−QXL _n(o-1) ′ △QXL _n(o-1) ′=QXL _{n(o-1 )} ′−QXL _n(o-2) ′ 〓 △QXL _n1 ′=QXL _n1 ′−QXC _n0 ′ △QXR _n1 ′=QXR _n1 ′−QXC _n0 ′ △QXR _n2 ′=QXR _n2 ′−QXR _n1 ′ 〓 △ Difference output expressed as QXR _no ′=QXR _no ′−QXR _n(o-1) ′ △QXL _no ′, △QXL _n(o-1) ′…
…QXL _n1 ′, △QXR _n1 ′, △QXR _n2 ′……
Get QXR _no ′.

In addition, the above-mentioned differential output △QXL _n1 ′ ~ QXL _no ′ is
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the difference output △QXL _n1 ′ side to the difference output △QXL _no ′ side, multiple difference outputs with positive values are obtained sequentially, and then difference outputs with a value of zero are obtained. The position on the array where the first difference output obtained (this is defined as ΔQXL _n ′) is obtained is determined.

Then _{, an} output (this is
Let WXL _n ′) be memorized.

Also, when looking at the above array sequentially from the difference output △QXR _n1 ′ side to the difference output △QXR _no ′ side, similarly, after a plurality of difference outputs with positive values are sequentially obtained,
The position on the array where the difference output (denoted as ΔQXR _n ′) at which the difference output with a value of zero is obtained first is obtained is determined.

Then, _output (this _is
Let WXR _n ′) be memorized.

Then, the output WXL _n ′ representing the array length mentioned above
and WXR _n ', an output MX n _' expressed as MX _n '=WXL _n '+WXR _n ' is obtained, stored, and outputted as a pulse HX _n ' as shown in FIG. 7B.

Further, the above-mentioned arithmetic processing circuit 51 outputs the above-mentioned second output QXL _(n-1)o ′ to QXL _(n-1)1 ′,
Store QXC _(n-1)0 ′, QXR _(n-1)1 ′~ _{QXR (n-1)o} ′,
And △QXL _(n-1)o ′=QXL _(n-1)o ′ −QXL _(n-1)(o-1) ′ △QXL _(n-1)(o-1) ′=QXL _{(n -1)(o-1)} ′ −QXL _(n-1)(o-2) ′ 〓 △QXL _(n-1)1 ′=QXL _(n-1)1 ′−QXC _(n-1)0 ′ △QXR _(n-1)1 ′=QXR _(n-1)1 ′−QXC _(n-1)0 ′ △QXR _(n-1)2 ′=QXR _(n-1)2 ′−QXR _{(n- 1)1} ′ 〓 △QXR _(n-1)o ′=QXR _(n-1)o ′ −QXR _(n-1)(o-1) ′ The difference output △QXL _(n-1)o ′ ,△
QXL _(n-1)(o-1) ′……QXL _(n-1)1 ′, △QXR _(n-1)1 ′,
△QXR _(n-1)2 ′...QXR _(n-1)o ′ is obtained.

In addition, the differential output △QXL _(n-1)1 ′~
Store QXL _(n-1)o ′ in sequence in their order.

Then, when looking at the array sequentially from the difference output △QXL _(n-1)1 ' side to the difference output △QXL _(n-1)o ' side, multiple difference outputs with positive values can be obtained sequentially. After that, the difference output at the value of zero is the first difference output obtained (this is △
Determine the position on the resulting array of QXL _n-1 ′).

Then, output representing the array length from the position on the array where the difference output △QXL n _{- 1} ′ is obtained to the position on the array where the difference output △QXL _n-1 ′).

In addition, the above array can be expressed as the difference output △QXR _(n-1)1 ′
When looking sequentially from the differential output △QXR _(n-1)o ′ side,
Similarly, after multiple difference outputs with positive values are obtained sequentially, the difference output with a value of _zero is obtained first. Determine the location of.

Then, output representing the array length from the position on the array where the difference output △QXR n _{- 1} ′ is obtained to the position on the array where the difference output ΔQXR _n-1 ′).

And the output representing the array length mentioned above
From WXL _n-1 ′ and WXR _n-1 ′, MX _n-1 ′=
Output expressed as WXL _n-1 ′ + WXR _n-1 ′
MX _n-1 ' is obtained, stored, and a pulse HX _n-1 ' is output as shown in FIG. 7B.

Further, the arithmetic processing circuit 51 described above outputs the third output QXL _(n-2)o ′ to QXL _(n-2)1 ′,
QXC _(n-2)0 ′, QXR _(n-2)1 ′～QXR _(n-2)o ′; 4th output QXL _(n-3)o ′～QXL _(n-3)1 ′QXC _(n-3)0 ′,
The same operation as described above is performed for QXR _(n-3)1 ′ to QXR _(n-3)o ′;...

Furthermore, the arithmetic processing circuit 51 described above outputs the m-th outputs QXL _1o ′ to QXL ₁₁ ′,
Store QXC ₁₀ ′, QXR ₁₁ ′ ~ QXR _1o ′, and then △QXL _1o ′=QXL _1o ′−QXL _1(o-1) ′ △QXL _1(o-1) ′=QXL _{1(o-1 )} ′−QXL _1(o-2) ′ 〓 △QXL ₁₁ ′=QXL ₁₁ ′−QXC ₁₀ ′ △QXR ₁₁ ′=QXR ₁₁ ′−QXC ₁₀ ′ △QXR ₁₂ ′=QXR ₁₂ ′−QXR ₁₁ ′ 〓 △ Difference output expressed as QXR _1o ′=QXR _1o ′−QXR _1(o-1) ′ △QXL _1o ′, △QXL _1(o-1) ′…
...QXL ₁₁ ′, △QXR ₁₁ ′, △QXR ₁₂ ′...QXR _1o ′ are obtained.

In addition, the differential output △QXL ₁₁ ′ to QXL _1o ′ mentioned above is
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the difference output △QXL ₁₁ ' side to the difference output △QXL _1o ' side, multiple difference outputs with positive values are obtained in sequence, and then difference outputs with a value of zero are obtained. Determine the position on the array where the first difference output (denoted as △QXL ₁ ') is obtained.

Then, _an output (this _is
WXL ₁ ′) is memorized.

Furthermore, when looking at the above-mentioned array sequentially from the differential output △QXR ₁₁ ′ side to the differential output △QXR _1o ′ side, similarly, after a plurality of differential outputs with positive values are sequentially obtained,
Determine the position on the array where the difference output (which is defined as △QXR ₁ ') where the difference output with a value of zero is obtained first is obtained.

Then, _an output (this _is
WXR ₁ ′) is memorized.

And the output representing the array length mentioned above
From WXL ₁ ′ and WXR ₁ ′, MX ₁ ′=WXL ₁ ′+
Obtain the output MX ₁ ′ represented by WXR ₁ ′, store it, and pulse as shown in FIG. 7B.
Output HX ₁ ′.

Further, the above-mentioned arithmetic processing circuit 51 outputs the above-mentioned (m+1)th output QXL _0o to QXL ₀₁ ,
Store QXC ₀₀ , QXR ₀₁ ~ QXR _0o , and then △QXL _0o = QXL _0o −QXL _0(o-1) △QXL _0(o-1) = QXL _0(o-1) −QXL _{0(o- 2)} Difference output expressed as 〓 △QXL ₀₁ = QXL ₀₁ −QXC ₀₀ △QXR ₀₁ = QXR ₀₁ −QXC ₀₀ △QXR ₀₂ = QXR ₀₂ −QXR ₀₁ 〓 △QXR _0o = QXR _0o −QXR _0(o-1) △QXL _0o , △QXL _0(o-1) ...QXL ₀₁ , △
QXR ₀₁ , △QXR ₀₂ ... Obtain QXR _0o .

In addition, the above-mentioned differential output △QXL ₀₁ ~ QXL _0o ,
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the difference output △QXL ₀₁ side to the difference output △QXL _0o side, after multiple difference outputs with positive values are obtained sequentially, the difference output with a value of zero is obtained first. Determine the position on the array where the difference output obtained (this is set as △QXL ₀ ) is obtained.

Then, the output representing the array length from the position on the array where the difference output △QXL ₀ is obtained to the position on the array where the difference output △QXL ₀₁ is obtained (this is assumed to be WXL ₀ ) is memorized. do.

Similarly, when looking at the above arrangement sequentially from the differential output △QXR ₀₁ side to the differential output △QXR _0o side,
After several difference outputs with positive values are obtained sequentially, the difference output with a value of zero is obtained first (this is called △
QXR ₀ )) determines the position on the resulting array.

Then, _{output (} this is
WXR ₀ ) is memorized.

Then, from the outputs WXL ₀ and WXR ₀ representing the above-mentioned array lengths, an output MX ₀ represented by MX ₀ =WXL ₀ +WXR ₀ is obtained and stored. Then, as shown in FIG. 7B, a pulse HX ₀ is output.

Furthermore, the above-mentioned arithmetic processing circuit 51 outputs the above-mentioned (m+2)th output QXL _1o to QXL ₁₁ ,
Store QXC ₁₀ , QXR ₁₁ ~ QXR _1o , and then △QXL _1o = QXL _1o −QXL _1(o-1) △QXL _1(o-1) = QXL _1(o-1) −QXL _{1(n- 2)} Difference output expressed as 〓 △QXL ₁₁ = QXL ₁₁ −QXC ₁₀ △QXR ₁₁ = QXR ₁₁ −QXC ₁₀ △QXR ₁₂ −QXR ₁₂ −QXR ₁₁ 〓 △QXR _1o = QXR _1o −QXR _1(o-1) △QXL _1o , △QXL _1(o-1) ……
QXL ₁₁ , △QXR ₁₁ , △QXR ₁₂ ... Obtain QXR ₁₂ .

In addition, the above-mentioned differential output △QXL ₁₁ ~ QXL _1o ,
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the differential output △QXL ₁₁ side to the differential output △QXL _1o side, after multiple differential outputs with positive values are obtained sequentially, the differential force with a value of zero is obtained first. Obtained difference output (let this be △QXL ₁ )
Determine the position on the resulting array.

Then, _output (this _is
WXL ₁ ).

Similarly, when looking at the above arrangement sequentially from the differential output △QXR ₁₁ side to the differential output △QXR _1o side,
After several difference outputs with positive values are obtained sequentially, the difference output with a value of zero is obtained first (this is called △
QXR ₁ ) determines the position on the resulting array.

Then, an output representing the array length from the position on the array where the difference output ΔQXR ₁ is obtained to the position on the array where the difference output ΔQXR ₁₁ is obtained (this is referred to as WXR ₁ ) is stored.

Then, from the outputs WXL ₁ and WXR ₁ representing the above-mentioned array lengths, an output MX ₁ represented by MX ₁ =WXL ₁ +WXR ₁ is obtained and stored. and the seventh
Output pulse HX ₁ as shown in Figure B.

Further, the arithmetic processing circuit 51 described above outputs the (m+3)th output Q×L _2o to Q×L ₂₁ , Q×
C ₂₀ , Q×R ₂₁ ~Q×R _2o ;(m+4)th output Q×L _3o ~Q×L ₃₁ ,Q×C ₃₀ ;Q×R ₃₁ ~Q×
Regarding R _3o ;..., the same operation as described above is performed.

Furthermore, the above-mentioned arithmetic processing circuit 51 outputs the above-mentioned (2m+1)th output Q×L _no ~QXL _n1 ,
Memorize QXC _n0 , QXR _n1 ~ QXR _no , and then △QXL _no = QXL _no −QXL _n(o-1) △QXL _n(o-1) = QXL _n(o-1) −QXL _{n(o- 2)} 〓 △QXL _n1 ＝QXL _n1 −QXC _n0 △QXR _n1 ＝QXR _n1 −QXC _n0 △QXR _n2 ＝QXR _n2 −QXR _n1 〓 △QXR _no ＝QXR _no −QXR _n(o-1) Difference output expressed as △QXL _no , △QXL _n(o-1) ……
QXL _n1 , △QXR _n1 , △QXR _n2 ... Obtain QXR _no .

In addition, the differential output △QXL _n1 ~QXL _no ′ mentioned above is
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the difference output △QXL _n1 side to the difference output △QXL _no side, multiple difference outputs with positive values are obtained sequentially, and then the difference output with a value of zero is obtained first. Determine the position of the obtained difference output (this is ΔQXL _n ) on the obtained array.

Then, _{output (} this is
Let WXL _n ) be memorized.

Similarly, when looking at the above arrangement sequentially from the differential output △QXR _n1 side to the differential output △QXR _no side,
After several difference outputs with positive values are obtained sequentially, the difference output with a value of zero is obtained first (this is called △
Determine the position on the obtained array of QXR _n ).

Then, an output representing the array length from the position on the array where the difference output ΔQXR _n is obtained to the position on the array where the difference output ΔQXR _n1 is obtained (this is referred to as WXR _n ) is stored.

And the output representing the array length mentioned above
From WXL _n and WXR _n , MX _n = WXL _n + WXR _n
Obtain the output MX expressed by
As shown in Figure B, a pulse HX _n is output.

As described above, the pulses HX _n ′, HX _n-1 ′...HX ₁ ′, sequentially obtained from the arithmetic processing circuit 51
HX ₀ ', HX ₁ , HX _{2 .} . . HX _n are supplied to the above-mentioned motor 35 via the motor drive circuit 53.

The motor 35 generates pulses HX _n ′, HX _n-1 ′, ...
HX ₁ ′, HX ₀ , HX ₁ , HX _{2 .} . . Each time HX _n is obtained, step rotation is performed in the forward direction. From the relative position with respect to the holder 23, which coincides with the line LX _n ', along the direction orthogonal to the above-mentioned line bb, it sequentially moves in steps toward the line LX _n by the above-mentioned distance e.

By such sequential step movement of the movable platen 22, the above-mentioned line c-c changes to the above-mentioned line LX _n '
From the relative position with the holding body 23 that matches,
Sequentially, the lines LX _n-1 ′, LX _n-2 ′……LX ₁ ′, LX ₀ , LX ₁
...A relationship matching LX _n is obtained.

By the way, the output WL _n ′ of the output MX _n ′ mentioned above is
It represents the length of the indentation 3 on the sample 2 from the center position O of the indentation 3 to the side edge on the point PX' side on the line LX _n ' mentioned above.

The reason is that the output WL _n ′ is the difference output △
From the position on the array where QXL _n ′ is obtained, the difference output △
This is the output representing the array length up to the position on the array where QXL _n1 ′ is obtained. On the other hand, the differential output △QXL _n ′ is
When the difference outputs △QXL _n1 ′ to QXL _no ′ are sequentially stored in an array, the array is sequentially viewed from the difference output △QXL′ side to the difference output △QL _no ′ side, and the difference outputs with positive values are are obtained sequentially, and the difference output at a value of zero is the first difference output obtained. Therefore, the differential output △
The positions on the array where QXL _n ′ can be obtained are shown in Figure 4 C and D, and the general outputs S _o ′, S _o-1 ′...S ₁ ′, S ₀ ,
From the above description of _the levels _{of S 1 , S 2} . This is because

In addition, the output WXR _n ′ of the output MX _n ′ mentioned above is
For the same reason as mentioned above, a point from the center position of the indentation 3 on the above-mentioned line LX _n ' of the indentation 3 of the sample 2
It represents the length to the side edge on the PX side.

Therefore, the above-mentioned output MX _n ' represents the length of the indentation 3 on the above-mentioned line LX _n '.

Furthermore, the above-mentioned outputs MX _n-1 ′, MX _n-2 ′...
MX ₁ ′, MX ₀ , MX ₁ , MX ₂ ...MX _n corresponds to the above-mentioned lines LX _n-1 ′, LX _n-2 ′, ...LX of the indentation 3, respectively, for the same reason as described above. ₁ ′, LX ₀ , LX ₁ ,
LX ₂ ...represents the length on LX _n .

The arithmetic processing circuit 51 also processes the above-mentioned pulses.
HX _n ′, HX _n-1 ′, …HX ₁ ′, HX ₀ , HX ₁ , HX ₂
...After outputting HX _n , as shown in Figure 7C,
Outputs one switching pulse PXW.

This switching pulse PXW is the motor drive circuit 5
4.

On the other hand, the motor drive circuit 54 is connected to the switch 3 which is engaged with the engagement pin 38 of the holder 23 described above.
9 and 39' are connected.

The switch 39' is configured so that the above-mentioned holder 23
Since it is in the rotational position, the switching pulse mentioned above
When PXW is obtained, it is operating.

When the above-mentioned switching pulse PXW is supplied while the switch 39' is in operation, the motor drive circuit 54 sequentially outputs the pulses KX as shown in FIG. 7D.

This sequential pulse KX... is supplied to the motor 30 mentioned above.

The motor 30 is sequentially supplied with pulses KX and rotates in steps in the forward direction. Therefore, the holding body 23 rotates in the forward direction.

Then, the holding body 23
8 rotates until it engages with the switch 39 described above, the switch 39 is activated.

Therefore, the above-described pulse KX from the motor drive circuit 54 is no longer obtained, the rotation of the motor 30 is stopped, and the rotation of the holder 23 is accordingly stopped.

When the rotation of the holding body 23 stops, the solid-state imaging devices E _o ′ to E ₁ ′ of the one-dimensional scanning imaging device 21 described above
The holder 23 has an arrangement line c-c of E ₀ , E ₁ to _{E o} that approximately coincides with the above-mentioned line LY _n ' in the sample 2.
It is assumed that the rotating position relative to the sample 2 (this will be referred to as the second rotating position) is maintained.

As just described, when the holding body 23 is in the second rotational position, the above-mentioned array line c-c is
When _the line LY _n ' on the sample 2 is approximately coincident with the line LY n ' mentioned above, the above-mentioned outputs S _o ' to S 1 ', S ₀ , S ₁ obtained sequentially for (2m+1) scans from time t ₃ ~S _o ,
As shown in FIG. 8A, the first output QYL _no ′ to QYL _n1 ′, as described above in FIG. 7A,
QYC _n0 ′, QYR _n1 ′～QYR _no ′; 2nd output
QYL _(n-1)o ′〜QYL _(n-1)1 ′, QYC _(n-1)0 ′,
QYR _(n-1)1 ′〜QYR _(n-1)o ′；……mth output
QYL _1o ′〜QYL ₁₁ ′，QYC′ ₁₀ ，QYR ₁₁ ′〜
QYR _1o ′; (m+1)th output QYL _0o ~
QYL ₀₁ , QYC ₀₀ , QYR ₀₁ ~ QYR _0o ;th (m+2)
Second output QYL _1o ~ QYL ₁₁ , QYC ₁₀ , QYR ₁₁ ~
QYR _1o ; (m+3)th output QYL _2o ~
QYL ₂₁ , QYC ₂₀ , QYR ₂₁ ~ QYR _2o ;...th (2m
+1) th output QYL _no ~QYL _n1 , QYC _n0 ,
Set QYR _n1 to QYR _no .

At that time, the above-mentioned arithmetic processing circuit 51 outputs the above-mentioned first output QYL _no ′ to QYL _n1 ′,
Remember QYC _n0 ′, QYR _n1 ′〜LYR _no ′, and △QYL _no ′=QYL _no ′−QYL _o(o-1) ′ △QYL _n(o-1) ′=QYL _{n(o-1 )} ′ −QYL _n(o-2) ′ 〓 △QYL _n1 ′=QYL _n1 ′−QYC _n0 ′ △QYR _n1 ′=QYR _n1 ′−QYC _n0 ′ △QYR _n2 ′=QYR _n2 ′−QYR _n1 ′ 〓 △ QYR _no ′=QYR _no ′−QYR _n(o-1) ′ Difference output △QYL _no ′, △QYL _n(o-1) ′…
…QYL _n1 ′, △QYR _n1 ′, △QYR _n2 ′……QYR _no
get.

In addition, the difference output △QYL′ _n1 〜QYL _no ′ mentioned above is
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the difference output △QYL _n1 ′ side to the difference output △QYL _no ′ side, multiple difference outputs with positive values are obtained sequentially, and then difference outputs with a value of zero are obtained. is the first difference output obtained (this can be expressed as △QYL _n ′
) is determined on the resulting array.

Then, output representing the array length from the position on the array where the difference output △QYL _n ′ is obtained to the array position where the difference output △QYL _n1 ′ is obtained (this can be expressed as WYL
m′) is stored.

Also, when looking at the above array sequentially from the differential output △QYR _n1 ′ side to the differential output △QYR _no ′ side, similarly, after a plurality of differential outputs with positive values are sequentially obtained,
The position on the array where the difference output (denoted as ΔQYR _n ′) where the difference output with a value of zero is obtained first is determined.

Then _{, output} (this is
Let WYR _n ′) be memorized.

Then, the output WYL _n ′ representing the array length mentioned above
and WYR _n ', an output YM _n ' expressed as MX _n '=WYL _n '+WYR _n ' is obtained, which is stored and a pulse HY _n ' is outputted as shown in FIG. 8B.

Further, the above-mentioned arithmetic processing circuit 51 outputs the above-mentioned second output QYL _(n-1)o ′ to QYL _(n-1)1 ′,
Memorize QYC _(n-1)0 ′, QYR _(n-1)1 ′〜QYR _(n-1)o ′,
And △QYL _(n-1)o ′=QYL _(n-1)o ′ −QYL _(n-1)(o-1) ′ △QYL _(n-1)(o-1) ′=QYL _{(n -1)(o-1)} ′ −QYL _(n-1)(o-2) ′ 〓 △QYL _(n-1)1 ′=QYL _(n-1)1 ′ −QYC _(n-1)0 ′ △QYR _(n-1)1 ′=QYR _(n-1)1 ′ −QYC _(n-1)0 ′ △QYR _(n-1)2 ′=QYR _(n-1)2 ′ −QYR _{(n- 1)1} ′ 〓 △QYR _(n-1)o ′=QYR _(n-1)o ′ −QYR _(n-1)(o-1) ′ The difference output △QYRL _(n-1)o ′ ,△QYL _{(n-1)
(o−1)} ′……QYL _(n-1)1 ′, △QYR _(n-1)1 ′, △
QYR _(n-1)2 ′...QYR _(n-1)o ′ is obtained.

In addition, the differential output △QYL _(n-1)1 ′~
Store QYL _(n-1)o ′ in sequence in that order.

Then, when looking at the array sequentially from the difference output △QYL _(n-1)1 ′ side to the difference output △QYL _(n-1)o ′ side, multiple difference outputs with positive values can be obtained sequentially. After that, the difference output at the value of zero is the first difference output obtained (this is △
Determine the position on the resulting array of QYL _n-1 ′).

Then, _output ( _{WYL n-1} ′).

In addition, the above array can be expressed as the difference output △QYR _(n-1)1 ′
When looking sequentially from the side to the differential output △QYR _(n-1)o ′ side,
Similarly, after multiple difference outputs with positive values are obtained sequentially, the difference output with a value of _zero is obtained first. Determine the location of.

Then, _{output (} Let this be WYR _n-1 ′).

And the output representing the array length mentioned above
From WYL′ _n-1 and WYR _n-1 ′, MY′ _n-1 =
Output MY _n-1 expressed as WYL _n-1 ′+WYR _n-1 ′
is obtained, stored, and outputs a pulse HY _n-1 ' as shown in FIG. 8B.

Further, the arithmetic processing circuit 51 described above outputs the third output QYL _(n-2)o ′ to QYL _(n-2)1 ′,
QYC _(n-2)0 ′, QYR _(n-2)1 ′～QYR _(n-2)o ′; 4th output QYL _(n-3)o ′～QYL _(n-3)1 ′, QYC _(n-3)0 ′,
Regarding QYR _(n-3)1 ′ to QYR _(n-3)o ′;..., the same operation as described above is performed.

Furthermore, the arithmetic processing circuit 51 described above outputs the m-th output QYL _1o ′QYL ₁₁ ′, QYC ₁₀ ′,
Remember QYR ₁₁ ′~QYR _1o ′, and then △QYL _1o ′=QYL _1o ′−QYL _1(o-1) ′ △QYL _1(o-1) ′=QYL _1(o-1) ′−QYL _1(o-2) ′ 〓 △QYL ₁₁ ′=QYL ₁₁ ′−QYC ₁₀ ′ △QYR ₁₁ ′=QYR ₁₁ ′−QYC ₁₀ ′ △QYR ₁₂ ′=QYR ₁₂ ′−QYR ₁₁ ′ 〓 〓 〓 △QYR′ _1o = QYR _1o ′−QYR _1(o-1) ′ Difference output △QYL _1o ′, △QYL _1(o-1) ′…
...QYL ₁₁ ′, △QYR ₁₁ ′, △QYR ₁₂ ′...QYR _1o ′ are obtained.

In addition, the difference output △QYL ₁₁ ′ to QYL _1o ′ mentioned above is
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the difference output △QYL ₁₁ ′ side to the difference output △QYL _1o ′ side, multiple difference outputs with positive values are obtained sequentially, and then difference outputs with a value of zero are obtained. Determine the position on the array where the first difference output (denoted as △QYL ₁ ') is obtained.

Then, _an output (this _is
Let WYL ₁ ′) be memorized.

Furthermore, when looking at the above array sequentially from the differential output △QYR ₁₁ ′ side to the differential output △QYR _1o ′ side, similarly, after a plurality of differential outputs with positive values are sequentially obtained,
The position on the array where the difference output (which is defined as ΔQYR ₁ ') where the difference output with a value of zero is obtained first is determined.

Then, _an output (this _is
WYR ₁ ′) is memorized.

And the output representing the array length mentioned above
From WYL ₁ ′ and WYR ₁ ′, MY ₁ ′=WYL ₁ ′+
Obtain the output MY′ represented by WYR ₁ ′, store it, and generate the pulse as shown in Figure 8B.
Output HY ₁ ′.

Further, the above-mentioned arithmetic processing circuit 51 outputs the above-mentioned (m+1)th output QYL _0o to QYL ₀₁ ,
Store QYC ₀₀ , QYR ₀₁ ~ QYR _0o , and then △QYL _0o = QYL _0o −QYL _0(o-1) △QYL _0(o-1) = QYL _0(o-1) −QYL _{0(o- 2)} 〓 △QYL ₀₁ ＝QYL ₀₁ −QYC ₀₀ △QYR ₀₁ ＝QYR ₀₁ −QYC ₀₀ △QYR ₀₂ ＝QYR ₀₂ −QYR ₀₁ 〓 △QYR _0o ＝QYR _0o −QYR _0(o-1) Difference output △QYL _0o , △QYL _0(o-1) ...QYL ₀₁ , △
QYR ₀₁ , △QYR ₀₂ ... Obtain QYR _0o .

In addition, the difference output △QYL ₀₁ ~QYL _0o mentioned above is
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the difference output △QYL ₀₁ side to the difference output △QYL _0o side, after multiple difference outputs with positive values are obtained sequentially, the difference output with a value of zero is obtained first. Determine the position on the array where the difference output obtained (this is set as △QYL ₀ ) is obtained.

Then _, output (this _is
WYL ₀ ) is memorized.

Similarly, when looking at the above arrangement sequentially from the differential output △QYR ₀₁ side to the differential output △QYR _0o side,
After several difference outputs with positive values are obtained sequentially, the difference output with a value of zero is obtained first (this is called △
Determine the position on the array from the obtained QYR ₀ ).

Then, _{output (} this is
WYR ₀ ) is memorized.

Then, from the outputs WYL ₀ and WYR ₀ representing the above-mentioned array lengths, an output MY ₀ represented by MY ₀ =WYL ₀ +WYR ₀ is obtained and stored. Then, as shown in FIG. 8B, a pulse HY ₀ is output.

Further, the arithmetic processing circuit 51 described above outputs the (m+2)th output QYL _1o to QYL ₁₁ ,
Memorize QYC ₁₀ , QYR ₁₁ ~ QYR _1o , and then △QYL _1o = QYL _1o −QYL _1(o-1) △QYL _1(o-1) = QYL _1(o-1) −QYL _{1(n- 2)} 〓 △QYL ₁₁ ＝QYL ₁₁ −QYC ₁₀ △QYR ₁₁ ＝QYR ₁₁ −QYC ₁₀ △QYR ₁₂ ＝QYR ₁₂ −QYR ₁₁ 〓 △QYR _1o ＝QYR _1o −QYR _1(o-1) Difference output △QYL _1o , △QYL _1(o-1) ...QYL ₁₁ , △
QYR ₁₁ , △QYR ₁₂ ... Obtain QYR _1o .

In addition, the above-mentioned difference output △QYL _1o ~ QYL _1o is
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the differential output △QYL ₁₁ side to the differential output △QYL _1o side, after multiple differential outputs with positive values are obtained sequentially, the differential output with a value of zero is obtained first. Determine the position on the array where the obtained difference output (this is set as △QYL ₁ ) is obtained.

Then, _output (this _is
WYL ₁ ) is memorized.

Similarly, when looking at the above arrangement sequentially from the differential output △QYL ₁₁ side to the differential output △QYL _1o side,
After several difference outputs with positive values are obtained sequentially, the difference output with a value of zero is obtained first (this is called △
QYR ₁ )) determines the position on the resulting array.

Then, an output representing the array length from the position on the array where the difference output ΔQYR ₁ is obtained to the position on the array where the difference output ΔQYR ₁₁ is obtained (this is referred to as WYR ₁ ) is stored.

Then, from the outputs WYL ₁ and MYR ₁ representing the above-mentioned array lengths, an output MY ₁ represented by MY ₁ =WYL ₁ +MYR ₁ is obtained and stored. and the eighth
Output pulse HY ₁ as shown in Figure B.

Further, the arithmetic processing circuit 51 described above outputs the (m+3)th output QYL _2o to QYL ₂₁ , QYC ₂₀ ,
QYR ₂₁ ~ QYR _2o : (m+4)th output
QYL _3o ~QYL ₃₁ , QYC ₃₀ :QYR ₃₁ ~ _{QYR 3o} :...
Regarding..., the same operation as described above is performed.

Furthermore, the above-mentioned arithmetic processing circuit 51 outputs the above-mentioned (2m+1)th output QYL _no to QYL _n1 ,
Memorize QYC _n0 , QYR _n1 ~ QYR _no , and then △QYL _no = QYL _no −QYL _n ( _o-1 ) △QYL _n ( _o-1) = QYL _n(o-1) −QYL _{n(o- 2)} 〓 △QYL _n1 ＝QYL _n1 −QYC _n0 △QYR _n1 ＝QYR _n1 −QYC _n0 △QYR _n2 ＝QYR _n2 −QYC _n1 〓 △QYR _no ＝QYR _no −QYR _n(o-1) Difference output △QYL _no , △QYL _n(o-1) …
QYL _n1 , △QYR _n1 , △QYR _n2 ... Obtain QYR _no .

Also, the difference output △QYL _n1 〜QYL _no ′ mentioned above is
They are sequentially arranged and stored in that order.

Then, when looking at the array sequentially from the difference output difference output △QYL ₁ side to the difference output △QYL _no side, after multiple difference outputs with positive values are obtained sequentially, the difference output with a value of zero is obtained. Determine the position on the array where the first difference output (denoted as ΔQYL _n ) is obtained.

Then, _output (this _is
Let WYL _n ) be memorized.

Similarly, when looking at the above arrangement sequentially from the differential output △QYR _n1 side to the differential output △QYR _no side,
After several difference outputs with positive values are obtained sequentially, the difference output with a value of zero is obtained first (this is called △
Determine the position on the resulting array of QYR _n ).

Then, an output representing the array length from the position on the array where the difference output ΔQYR _n is obtained to the position on the array where the difference output ΔQYR _n1 is obtained (this is assumed to be WYR _n ) is stored.

And the output representing the array length mentioned above
From WYL _n and WYR _n , MY _n = WYL _n + WYR _n
Obtain the output MY expressed by
As shown in Figure B, a pulse HY _n is output.

As described above, the pulses HY _n ′, HY _n-1 ′...HY ₁ ′, sequentially obtained from the arithmetic processing circuit 51
HY ₀ , HY ₁ , HY ₂ . . . HY _n are supplied to the above-mentioned motor 35 via the motor drive circuit 53.

The motor 35 has Pars HY _n ′, HY _n-1 ′,...
...HY ₁ ′, HY ₀ , HY ₁ , HY ₂ ... Each time HY _n is obtained, step rotation is performed in the forward direction, and accordingly,
From the relative position of the movable platen 22 to the holder 23, where the line c-c coincides with the point _LYn ', along the direction perpendicular to the line b-b, Steps are sequentially moved to the line LY _n side.

In this case, the movable platen 22 is moved in successive steps from the relative position with respect to the holder 23 where the above-mentioned line c-c coincides with the above-mentioned line LY _n ', to the line LY n-1 ', LY _n-1 ', LY _n-2 ′……LY ₁ ′, LY ₀ ′, LY ₁ ……
It is made to match LY _n .

By the way, the output WL _n ′ of the output MY _n ′ mentioned above is
It represents the length of the indentation 3 on the sample 2 from the center position O of the indentation 3 to the side edge on the point PY' side on the line LY _n ' mentioned above.

The reason is that the output WL _n ′ is the difference output △
From the position on the array where QYL _n ′ is obtained, the difference output △
QYL _n1 ′ is an output representing the array length up to the position on the array. On the other hand, the differential output △QYL _n ′ is
When the difference outputs △QYL _n1 ′ to QYL _no ′ are sequentially stored in an array, and the array is viewed sequentially from the difference output △QYL _n1 ′ side to the difference output △QL _no ′ side, it is After a plurality of values are obtained in sequence, the difference output with a value of zero is the first difference output obtained. Therefore, the differential output △
The positions on the array where QYL _n ′ can be obtained are shown in Figure 5 C and D, and the general outputs S _o ′, S _o-1 ′...S ₁ ′, S ₀ ,
S ₁ , S ₂ ... From the above description of the levels of S _o-1 and S _o , it is clear that they correspond to the side edge of the indentation 3 on the point PY' side on the line LY _n ' mentioned above. This is because

In addition, the output WYR _n ′ of the output MY _n ′ mentioned above is
For the same reason as mentioned above, a point from the center position of the indentation 3 on the above-mentioned line LY _n ' of the indentation 3 of the sample 2
It represents the length to the side edge on the PY side.

Therefore, the above-mentioned output MY _n ' represents the length of the impression 3 on the above-mentioned line LY _n '.

Furthermore, the above-mentioned outputs MY _n-1 ′, MY _n-2 ′...
...MY ₁ , MY ₀ , MY ₁ , MY ₂ ...... MY _n is the above-mentioned line LY _n-1 ′, LY _n-2 ′, ... of the indentation 3, respectively, for the same reason as mentioned above. LY ₁ ′, LY ₀ ,
LY ₁ , LY ₂ ......Represents the length on LY _n .

The arithmetic processing circuit 51 also processes the above-mentioned pulses.
HM _n ′, HY _n-1 , ...HY ₁ ′, HY ₀ , HY ₁ , HY ₂
After outputting HY _n , one switching pulse PYW is output as shown in FIG. 8C.

This switching pulse PYW is the motor drive circuit 5
4.

On the other hand, the motor drive circuit 54 is connected to the switch 3 which is engaged with the engagement pin 38 of the holder 23 described above.
9 and 39' are connected.

Since the above-mentioned holder 23 is in the second rotational position, the switch 39 receives the above-mentioned switching pulse.
When PYW is obtained, it is operating.

When the above-described switching pulse PYW is supplied while the switch 39 is in operation, the motor drive circuit 54 sequentially outputs the pulses KY as shown in FIG. 8D.

This sequential pulse KY... is supplied to the motor 30 mentioned above.

The motor 30 receives sequential pulses KY and rotates in steps in the forward direction. Therefore, the holding body 23 rotates in the forward direction.

Then, the holding body 23
8 is rotated until it engages with the above-mentioned switch 39', the switch 39' is activated.

Therefore, the above-mentioned pulse KY is no longer obtained from the motor drive circuit 54, the rotation of the motor 30 is stopped, and the rotation of the holder 23 is accordingly stopped.

When the rotation of the holding body 23 stops, the solid-state image sensors En′ to E ₁ ′ of the one-dimensional scanning imaging device 21 described above
A holder 23 in which the array line C-C of E ₀ , E ₁ to En approximately coincides with the above-mentioned line LX _n ' in the sample 2
, and returns to the first rotational position relative to the sample 2 .

As described above, the arithmetic processing circuit 51 stores the above-mentioned outputs MX _n ′ to _{MX n-1} ′, MX ₀ , MX 1 to MX _n , and also stores the above-mentioned outputs MY _{n ′} to MX n-1 ′, MX ₀ , MX 1 to MX n.
It remembers MY ₁ , MY ₀ , MY ₁ to _{MY n} .

The arithmetic processing circuit 51 outputs the above-mentioned outputs MX′ _n ~
Determine the output that takes the maximum value among MX ₁ ′, MX ₀ , MX ₁ to MX _n (this is designated as MX), and calculate that output.
Output MX. As mentioned above, this output MX is the output MX _n ′ ~ _{MX 1} ′, MX ₀ , MX ₁ ~
If MX _n is obtained, the output is MX ₀ .

Further, the arithmetic processing circuit 51 outputs the above-mentioned output.
The output that takes the maximum value among MY _n ′ to _{MY 1} ′, MY ₀ , MY ₁ to _{MY n} (this is set as MY) is determined, and that output MY is output. As mentioned above, this output MY is the output MY _n ′ ~ _{MY 1} ′, MY ₀ , MY ₁
If you get ~MY _n , the output is MY ₀ .

As is clear from the above, the output MX described above represents the length NX of the first diagonal line connecting the points PX and PX' of the indentation 3 on the sample 2.

In addition, as is clear from the above, the output MY mentioned above is the point PY and the point PY of the indentation 3 of the sample 2.
It represents the length NY of the second diagonal line connecting PY′.

As described above, according to the embodiment of the indentation type hardness meter according to the present invention, the lengths NX and NY of the first and second diagonal lines of the indentation 3 made on the sample 2 can be measured.

Therefore, the hardness of sample 2 can be measured from the lengths NX and NY.

In this case, according to the indentation type hardness meter according to the present invention described above, the indentation 3 made on the sample 2 is one-dimensionally scanned and imaged using the one-dimensional scanning imaging device 21, and from the imaging output, the indentation 3 is An output representing the first and second diagonal lengths is obtained.

Therefore, according to the indentation type hardness tester according to the present invention, a simple, compact, and inexpensive one-dimensional scanning imaging device can be used as the imaging device used to obtain the first and second diagonal length signals. It has the following characteristics.

Further, according to the indentation type hardness tester according to the present invention, since the one-dimensional scanning imaging device does not scan the indentation over the entire area of the indentation, the length signals of the first and second diagonals of the indentation can be obtained at high speed. can be obtained.

Further, the indentation type hardness tester according to the present invention has great features such as the simplicity of the entire device.

Furthermore, according to the indentation type hardness tester according to the present invention,
The imaging output obtained from the one-dimensional scanning imaging device is the output obtained by scanning and imaging the indentation in a focused state, so the diagonal length of the indentation can be accurately obtained, so the hardness of the sample can be accurately determined. Can be measured.

Furthermore, since the focus signal used to obtain the in-focus state is obtained from the output of the imaging device, the in-focus state can be easily obtained.

In the above description, an example was described in which the present invention is applied to an indentation type hardness tester that is designed to make a square pyramid-shaped indentation on a sample. The present invention can also be applied to a type hardness meter.

In addition, without departing from the spirit of the invention,
Various modifications may be made.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a mechanical system of an embodiment of the indentation type hardness tester according to the present invention. Second
The figure is a sectional view on the - line. FIG. 3 is a diagram showing an indentation made on a sample. FIG. 4A is a diagram for explaining the case of one-dimensional scanning imaging of a sample using a one-dimensional imaging device, and FIGS. 4B-
D is a waveform diagram illustrating a case where a sample is scanned one-dimensionally. FIG. 5 is a systematic connection diagram showing an example of an electrical system when the mechanical system of the embodiment of the indentation type hardness tester according to the present invention is used. FIG. 6, FIG. 7, and FIG. 8 are signal arrangement diagrams for explaining this. 1... Sample mounting table, 2... Sample, 3... Indentation,
4... Base, 5, 6... Cylindrical body, 7... Thread, 8...
... Gear, 9 ... Spiral shaft, 10 ... Motor for raising and lowering sample mounting table 1, 11 ... Rotating shaft of motor 10,
12, 13...Gear, 20...Imaging device mounting body,
21... one-dimensional scanning imaging device, 22... movable plate,
23... Holding body, 24... Cylindrical portion of holding body 23, 2
5...Ring part of the holding body 23, 26...Cylinder part of the holding body 23, 27...Plate part of the holding body 23, 28...Gear attached to the cylinder part 24, 29...Slit of the plate part 27 , 30... a motor that rotates the holding body 23, 3
1...Rotating shaft of motor 30, 32... Rotating shaft 31
33... A rod attached to the movable platen 22, 34... A main screw provided on the rod 33, 35... A motor for moving the movable platen 22, 36... Motor 35
rotational shaft, 37...screw provided on the rotational shaft 36, 3
8...Engagement pin planted in the holding body 23, 3
9, 39'...Switches operated by engagement of the engagement pin 38, Eo _' to _E1 ', _E0 , _E1 to _Eo ...Solid-state imaging device of the one-dimensional scanning imaging device 21, a ...Axis of the holding body 23, bb...A line perpendicular to the axis a, c
-c...Line on which the solid-state imaging devices Eo _' to _E1 ', _E0 , _E1 to _Eo are arranged, 40...Support, 41...Cylinder, 42...Extended from the cylinder 41 ring plate, d
...Axle of the cylinder 41, 43...Cylinder attached to and communicating with the cylinder 41, 44...Light source, 4
5, 47...lens, 46...half mirror, 5
0...Clock pulse generation circuit, PX, PX'...
Opposite points of the indentation 3, PY, PY'...Other opposing points of the indentation 3, LX ₀ ...Line passing through the points PX and PX', LY ₀ ...Line passing through the points PY and PY', O...
Intersection of LX ₀ and LY ₀ , LX ₁ ~ LX _n , LX′ ₁ ~ _{LX n} ′
...Line parallel to line LX ₀ , LY ₁ ~LY _n , LY ₁ ′ ~
LY _n ′...Line parallel to line LY ₀ , 51... Arithmetic processing circuit, 52, 53, 54... Motor drive circuit.

Claims (1)

[Scope of Claims] 1. A sample mounting table on which a sample with an indentation is placed; an imaging device mounting body mounting a scanning imaging device that scans and images the indentation made on the sample; means for sequentially scanning and imaging the indentation a plurality of U times by a scanning imaging device, and correspondingly causing the scanning imaging device to sequentially output a plurality of U imaging outputs; In response to outputting U scanning imaging outputs, a plurality of U scanning images are sequentially output.
U pulses are output, and using the plurality of U pulses, the scanning imaging device scans and images the indentation with the indentation in a focused state. The sample mounting table and the image pickup device frame are moved relative to the in-focus point position a plurality of U times from a relative reference position away from the in-focus position, thereby a means for relatively moving the sample mounting table and the imaging device frame to a position beyond the focal point; The pulse is used to move the sample mounting table and the imaging device frame relative to each other a plurality of U times in sequence from a position beyond the in-focus position toward the reference position. , means for relatively moving and returning to the reference position; detecting which number of imaging outputs among the plurality of U imaging outputs output from the scanning imaging device takes the maximum value; When the maximum value of the r-th imaging output is the maximum value among the maximum values of the plurality of U imaging outputs, the sample mounting table and the imaging device frame are relatively moved back to the reference position. After that, r pulses are sequentially generated, and using the r pulses, the sample mounting table and the imaging device frame are moved relative to the reference position toward the in-focus position r times in sequence. The sample mounting table and the imaging device frame are moved step by step.
A push-in type hardness tester comprising means for moving the focused point relatively to the focused position.