JPH0336751A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0336751A
JPH0336751A JP17239689A JP17239689A JPH0336751A JP H0336751 A JPH0336751 A JP H0336751A JP 17239689 A JP17239689 A JP 17239689A JP 17239689 A JP17239689 A JP 17239689A JP H0336751 A JPH0336751 A JP H0336751A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
manufacturing
pattern
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17239689A
Other languages
Japanese (ja)
Inventor
Toyoyuki Shimazaki
豊幸 嶋崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP17239689A priority Critical patent/JPH0336751A/en
Publication of JPH0336751A publication Critical patent/JPH0336751A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To flatten an interlayer film, etc., at low temperature or for a short time by employing a film with tension stress as a second film and heat-treating said film at a temperature where a first film gets fluid. CONSTITUTION:A pattern 2 is formed with polycrystalline silicon for example on one principal surface of a semiconductor substrate 1, on which pattern a PSG film including about 9wt.% phosphorus pentoxide for example is deposited as a first film 3 by CVD process. A molybdenum silicide film is formed on the first film 3 as a second film 4 by magnetron sputtering for example and heat-treated at 1000 deg.C in the nitrogen atmosphere for 5 minutes for example for flattening thereof. Thereupon, the PSG film 3 is fluid at 1000 deg.C and the molybdenum film 4 has tension stress at 1000 deg.C additionally to fluidity of the film itself, so that the fluidity is promoted for satisfactory flattening for a short time.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、段差を有するパターン上の絶縁被膜を平坦化
する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for planarizing an insulating coating on a pattern having steps.

従来の技術 従来の半導体装置の製造方法について第2図(a)〜(
C)の工程順断面図により説明する。
BACKGROUND ART Conventional method for manufacturing semiconductor devices FIGS.
This will be explained using step-by-step sectional views of C).

第2図(a)に示すように、半導体基板11の一生面上
にたとえば多結晶シリコンなどでパターン12を形成し
た。第2図(b)は前記パターン12上にシリコン酸化
膜(約9 w t%の五酸化リンを含む:PSGI]N
)13をCVD法により堆積させ、第2図(c)に示す
ように、例えば、窒素雰囲気中で1000℃30分の熱
処理により前記シリコン酸化膜13の段差部を平坦化し
た。
As shown in FIG. 2(a), a pattern 12 made of, for example, polycrystalline silicon was formed on the whole surface of the semiconductor substrate 11. As shown in FIG. FIG. 2(b) shows a silicon oxide film (containing about 9 wt% phosphorus pentoxide: PSGI) on the pattern 12.
) 13 was deposited by the CVD method, and the step portion of the silicon oxide film 13 was flattened by heat treatment at 1000° C. for 30 minutes in a nitrogen atmosphere, for example, as shown in FIG. 2(c).

発明が解決しようとする課題 従来の技術では、層間膜等の良好な平坦度を得るために
高温で長時間の熱処理が必要であり、例えば、MO8型
トランジスタのソース・ドレイン拡散層や、バイポーラ
型トランジスタのエミッタ拡散層に用いられている不純
物が半導体基板等へ拡散し、素子特性のバラツキや微細
化の妨げとなるという課題があった。
Problems to be Solved by the Invention Conventional technology requires heat treatment at high temperatures for a long time to obtain good flatness of interlayer films, etc. There has been a problem in that impurities used in the emitter diffusion layer of a transistor diffuse into a semiconductor substrate and the like, causing variations in device characteristics and hindering miniaturization.

本発明は、上記従来の課題を解決するもので、従来より
低温あるいは短時間で層間膜等の平坦化を実現すること
のできる半導体装置の製造方法を提供することを目的と
する。
The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can realize planarization of an interlayer film or the like at a lower temperature or in a shorter time than the conventional method.

課題を解決するための手段 本発明の半導体装置の製造方法は、層間絶縁膜等の第1
膜上に第2膜を形成する工程、前記第1膜及び第2膜を
熱処理する工程により構成されている。
Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention provides a first method for manufacturing a semiconductor device such as an interlayer insulation film.
The method includes a step of forming a second film on the film, and a step of heat-treating the first film and the second film.

作用 本発明の構成の内、第21]Iに引っ張り応力をもつ膜
を用い、第1膜が流動性となる温度で熱処理を行なうこ
とにより、従来第1膜自体の流動力でしか平坦化できな
かったのに対し、第1膜自体の流動力に加え、第2膜の
引っ張り応力で平坦化を促進でき、従来より短時間で良
好な平坦度が得られる。
Function In the structure of the present invention, by using a film having tensile stress in the 21st film I and performing heat treatment at a temperature at which the first film becomes fluid, flattening can be achieved only by the fluidity of the first film itself. In contrast, flattening can be promoted by the tensile stress of the second film in addition to the flow force of the first film itself, and good flatness can be obtained in a shorter time than conventionally.

実施例 以下、本発明の一実施例について、第1図(a)〜(d
)の工程順断面図に従って説明する。
EXAMPLE Below, an example of the present invention will be explained with reference to FIGS. 1(a) to (d).
) will be explained according to the step-by-step cross-sectional diagrams.

第1図(a)に示すように、半導体基板1の一生面上に
、たとえば、厚さ500nmの多結晶シリコンなどでパ
ターン2を形成した。第1図(b)は前記パターン2上
に第1膜3として、例えば、約9 w t%の五酸化リ
ンを含むPSG膜を800nmの厚さでCVD法により
堆積させた。第1図(c)は前記第1膜3上に第2膜4
として、例えば、マグネトロンスパッタ法によってモリ
ブデンシリサイド膜を200nm形成した。第1図(d
)は、例えば、窒素雰囲気中で1. OO0℃、5分の
熱処理をほどこし平坦化を行なった。この時、前記PS
G膜3は1000℃では流動性であり、膜自体の流動力
に加え、モリブデンシリサイド膜4が1000℃で引っ
張り応力を持つため、流動が促進され短時間に良好な平
坦化が行なわれる。
As shown in FIG. 1(a), a pattern 2 of polycrystalline silicon or the like having a thickness of 500 nm was formed on the entire surface of a semiconductor substrate 1. As shown in FIG. In FIG. 1(b), a PSG film containing, for example, about 9 wt% phosphorus pentoxide was deposited as a first film 3 on the pattern 2 to a thickness of 800 nm by the CVD method. FIG. 1(c) shows a second film 4 on the first film 3.
For example, a molybdenum silicide film with a thickness of 200 nm was formed by magnetron sputtering. Figure 1 (d
), for example, 1. A heat treatment was performed at OO0° C. for 5 minutes to flatten the surface. At this time, the PS
The G film 3 is fluid at 1000° C., and in addition to the fluidity of the film itself, the molybdenum silicide film 4 has tensile stress at 1000° C., which promotes fluidity and achieves good planarization in a short time.

なお、本実施例では第1膜3としてリンを含有したシリ
コン酸化膜、第2膜4としてモリブデンシリサイド膜を
用いたが、第1膜3としては熱処理により流動性となる
膜、第2膜4としては、熱処理時に引っ張り応力をもつ
膜を適当に選択することにより実現できる。また、熱処
理温度についても、第1膜3、第2膜4の膜種により適
当に設定すればよい。
In this example, a silicon oxide film containing phosphorus was used as the first film 3, and a molybdenum silicide film was used as the second film 4. This can be achieved by appropriately selecting a film that has tensile stress during heat treatment. Further, the heat treatment temperature may be appropriately set depending on the film types of the first film 3 and the second film 4.

本発明を眉間絶縁膜の平坦化に応用した場合は、上記実
施例にひき続き第2膜4を選択的に除去する工程を追加
するだけで容易に実現できる。
When the present invention is applied to flattening the glabellar insulating film, it can be easily realized by simply adding a step of selectively removing the second film 4 following the above embodiment.

発明の効果 本発明の半導体装置の製造方法により、従来より低温あ
るいは、短時間で層間膜等の平坦化ができ、不純物拡散
層の深さおよび、横方内拡がりを抑制し、MO8型トラ
ンジスタやバイポーラ型トランジスタの微細化、高密度
集積化を実現することが可能である。
Effects of the Invention The semiconductor device manufacturing method of the present invention allows interlayer films to be flattened at a lower temperature or in a shorter time than conventional methods, suppresses the depth and lateral expansion of impurity diffusion layers, and improves MO8 type transistors and It is possible to achieve miniaturization and high-density integration of bipolar transistors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)はそれぞれ本発明の一実施例を示
す半導体装置の製造工程を示す工程順断面図、第2図(
a)〜(c)は従来例の製造工程を示す工程順断面図で
ある。 1・・・・・・半導体基板、2・・・・・・多結晶シリ
コンなどのバタン、3・・・・・・第1膜、4・・・・
・・第2膜。
FIGS. 1(a) to 1(d) are process-order sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG.
a) to (c) are step-by-step sectional views showing manufacturing steps of a conventional example. 1... Semiconductor substrate, 2... Batten such as polycrystalline silicon, 3... First film, 4...
...Second membrane.

Claims (6)

【特許請求の範囲】[Claims] (1)半導体基板上の段差を有するパターン上に第1膜
を形成する工程と、前記第1膜上に熱処理する工程で引
っ張り応力をもつ第2膜を形成する工程、前記第1膜及
び第2膜を熱処理する工程とを備えた半導体装置の製造
方法。
(1) A step of forming a first film on a pattern having steps on a semiconductor substrate, a step of forming a second film having tensile stress in a heat treatment step on the first film, and a step of forming a second film having tensile stress on the first film and A method for manufacturing a semiconductor device, comprising a step of heat treating two films.
(2)第1膜が熱処理により流動性となることを特徴と
する請求項(1)記載の半導体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim (1), wherein the first film becomes fluid by heat treatment.
(3)第1膜がシリコン酸化膜であることを特徴とする
請求項(1)記載の半導体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim (1), wherein the first film is a silicon oxide film.
(4)シリコン酸化膜が、リン、ホウ素、ヒ素の少くと
も1種を含有していることを特徴とする請求項(3)記
載の半導体装置の製造方法。
(4) The method for manufacturing a semiconductor device according to claim (3), wherein the silicon oxide film contains at least one of phosphorus, boron, and arsenic.
(5)熱処理は第1膜が流動性となる温度以上で行なう
ことを特徴とする請求項(1)記載の半導体装置の製造
方法。
(5) The method for manufacturing a semiconductor device according to claim (1), wherein the heat treatment is performed at a temperature higher than a temperature at which the first film becomes fluid.
(6)熱処理は第2膜が流動性となる温度より低い温度
で行なうことを特徴とする請求項(1)記載の半導体装
置の製造方法。
(6) The method for manufacturing a semiconductor device according to claim (1), wherein the heat treatment is performed at a temperature lower than the temperature at which the second film becomes fluid.
JP17239689A 1989-07-04 1989-07-04 Manufacture of semiconductor device Pending JPH0336751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17239689A JPH0336751A (en) 1989-07-04 1989-07-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17239689A JPH0336751A (en) 1989-07-04 1989-07-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0336751A true JPH0336751A (en) 1991-02-18

Family

ID=15941162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17239689A Pending JPH0336751A (en) 1989-07-04 1989-07-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0336751A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213462A (en) * 1994-11-23 1996-08-20 Lg Semicon Co Ltd Method for forming wiring layer of semiconductor element

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5578546A (en) * 1978-12-11 1980-06-13 Toshiba Corp Manufacture of semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5578546A (en) * 1978-12-11 1980-06-13 Toshiba Corp Manufacture of semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213462A (en) * 1994-11-23 1996-08-20 Lg Semicon Co Ltd Method for forming wiring layer of semiconductor element

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