JPH0336769A - Thin film transistor, its manufacturing method, matrix circuit board and image display device using the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a thin film transistor used in an active matrix drive type image display device, and in particular to a thin film transistor in which the film quality of the gate insulating film is changed in the depth direction of the film, a method for manufacturing the same, and an active matrix circuit using the same. The present invention relates to a substrate and an image display device.

[Conventional technology]

A large number of thin film transistors formed in a matrix on an insulating substrate such as glass have been put to practical use as switching elements for active matrix circuit boards used in image display devices. FIG. 5(a) shows a cross-sectional structural diagram of a main part of an amorphous silicon thin film transistor that is currently most commonly used. In the figure, 1 is an insulating substrate such as a glass plate, 2 is a gate electrode made of a metal film such as a chromium film, 3 is a gate insulating film made of a silicon nitride film, etc., and 4 is a semiconductor made of an amorphous silicon film. 51 and 61 are n-type semiconductor films made of an amorphous silicon film doped with phosphorus, etc., and 52 and 62 are drain electrodes or source electrodes made of metal films such as aluminum films. An active matrix circuit board is completed by arranging them in a two-dimensional matrix, connecting the gate electrodes to form an I-th bus line, and connecting the drain electrodes to form a second bus line. Note that, for example, Japanese Patent Application Laid-open No. 181472/1983 can be cited as related to this type of thin film transistor.

[Problem M that the invention attempts to solve]

The above-mentioned prior art does not give any consideration to the workability of the gate insulating film, such as performing inclined etching on the inner wall of the hole when providing an opening in the gate insulating film for taking out an electrode. Therefore, as shown in FIG. 5(b), when connecting, for example, the source electrode 6 and the display pixel electrode 7 of the thin film transistor through the etching step (indicated by 3'') of the gate insulating film, this step 3 ' may cause a connection failure, or, as shown in FIG. 5(C), for example, a drain line (signal wiring) may be
9, there is a problem in that the wiring resistance at this stepped portion 3' increases, making it easy to break the wire. Therefore, an object of the present invention is to solve the above-mentioned problems of the conventional art. The third purpose of the manufacturing method is to
A fourth object is to provide an active matrix circuit board using the improved active matrix circuit board, and an image display device constructed using the improved active matrix circuit board.

[Means to solve the problem]

The first object of the present invention is to provide an electrode group comprising a gate electrode and other wiring and electrodes provided separately on the #fA edge plate substrate, and an electrode group that covers the electrode group. a gate insulating film formed, a semiconductor film pattern disposed to be located on at least the gate insulating film on the gate electrode, and a semiconductor film pattern disposed at both ends of the semiconductor film pattern so as to overlap with at least the gate electrode. a wiring conductor or the drain electrode in which at least one of the drain electrode and the source electrode and the other wiring electrode are electrically connected through an opening provided in the gate insulating film; and a wiring conductor electrically connected to at least one of the source electrodes and existing on an etched step provided in the gate insulating film, in which the gate insulating film is connected in a depth direction from the surface thereof. a gate insulating film whose etching rate substantially decreases as it moves away from the substrate side; This is achieved by a thin film transistor having a substantially gentle slope. Preferably, the gate insulating film is composed of a silicon-based insulating thin film, and hydrogen or oxygen is contained in the gate insulating film, and in the case of hydrogen, the content of hydrogen is large on the surface side of the insulating film and extends in the depth direction. This is achieved by a thin film transistor having a concentration gradient that gradually decreases, and in the case of oxygen, the concentration gradient is small on the surface side of the insulating film and gradually increases in the depth direction. In this way, a single insulating film may be provided with the property that the etching rate gradually decreases from the surface in the depth direction, or a multilayer structure as shown below may be used. That is, the gate insulating film has a multilayer structure with different etching rates, and the outermost insulating thin film that contacts the semiconductor pattern is a thin film with a high etching rate.
A thin film transistor may be formed by laminating thin films whose etching rate gradually decreases as it moves away from the substrate in the internal depth direction. Practically, this is preferable. In addition, when using this multilayer film, the number of layers constituting the gate insulating film may be any number as long as it is thick enough to function as a gate of a transistor in principle. Considering the equipment investment for film manufacturing equipment and the degree of freedom in selecting film forming conditions, it is practical to use 2 to 4 layers. The second object is to form an electrode group pattern having a gate electrode and other wiring electrodes on an insulating substrate when manufacturing the thin film transistor, and then to form a gate pattern so as to cover the electrode group. 1! In the process of forming the edge film, a plurality of #! films are arranged in series in order from the thin film with the lowest etching rate to the thin film with the highest etching rate. The process includes forming a film while sequentially moving the film forming chamber without breaking the vacuum, and then, after forming a thin film semiconductor pattern, the gate insulating film is coated with a fluorine compound gas using a predetermined resist mask pattern. providing an electrode extraction hole by dry etching and exposing a part of the electrode group provided on the insulating substrate;
A step in which a drain electrode and a source electrode are provided separately at both ends of the thin film semiconductor pattern, and the drain electrode is connected to a wiring electrode on the substrate through the electrode extraction hole, or at least one of the drain electrode and the source electrode. This is achieved by a method for manufacturing a thin film transistor comprising the steps of: and a step of causing an electrically connected wiring conductor to exist on an etching step provided in the gate insulating film. The gate insulating film is preferably a silicon-based insulator such as a silicon nitride film. The third object is to arrange a plurality of thin film transistors in a matrix on the same insulating substrate, connect the gate electrodes of each thin film transistor to form a first bus line,
This is achieved by a matrix circuit board that connects the drain electrode to a wiring electrode provided on the insulating substrate through an electrode extraction hole provided in the gate insulating film to form a second bus line. The fourth object is to provide a display pixel electrode group on the gate insulating film between the thin film transistors provided on the matrix circuit board, and connect each electrode terminal of the display pixel electrode group to the corresponding thin film transistor. An image display in which a counter electrode is connected to the source electrode and further faces the display pixel electrode group, and the gap between the display pixel electrode group and the counter electrode is filled with liquid crystal and sealed to form a display cell. This is achieved by the device. Note that the display pixel electrode may be provided in advance on the same surface as the gate electrode instead of being formed on the gate insulating film. In this case, the gate insulating film on the display pixel electrode is removed by etching and then electrically connected to the source electrode of the thin film transistor.

[Effect]

In the present invention, since the etching rate of the gate insulating film in contact with the semiconductor pattern is set higher than that in the depth direction of the lower layer, the amount of side etching in the upper layer of the gate insulating film is larger than that in the lower layer. This allows oblique etching of the gate insulating film.

【Example】

Example 1 An example of the present invention will be described below with reference to FIGS. 1 to 3. FIG. 1(a) shows a cross-sectional view of a thin film transistor to which the present invention is applied, and FIG. 1(b) shows the etching rate and gate insulation of a silicon nitride film used as a gate insulating film by dry etching using a fluorine compound gas. In Figure 0, which shows an outline of the profile of the hydrogen content in the film in the depth direction, 1 is an insulating substrate such as a glass substrate, 2 is a gate electrode made of a metal film such as chromium, and 3 is a gate electrode made of a metal film such as chromium. A gate insulating film made of a silicon-based insulating thin film, 4 a semiconductor film pattern made of an amorphous silicon film, 51 and 61 semiconductor films made of an n-type amorphous silicon film doped with phosphorus (P), 5
2 and 62 are metal films such as aluminum, 5 is a drain electrode, and 6 is a source electrode. The present invention is applied by changing the film quality of the gate insulating film 3 in the depth direction of the film, as shown in FIG. In this example, the N/S in the gate insulating film is increased as it gets closer and smaller as it gets farther away.
The conditions for forming the silicon nitride film were varied within a range that resulted in a film having an i ratio of 1.3 or more. By changing the hydrogen content in the film, the film density is changed, and the etching rate is given a distribution in the depth direction. Hereinafter, the manufacturing process of this thin film transistor will be explained with reference to FIG. FIG. 2(a) shows the manufacturing process flow of the thin film transistor shown in FIG. 1, and FIG. 2(b) shows the plasma CVD
(Chemical Vapor Deposit
FIG. 2 is a block diagram showing a case where a gate insulating film 3, an amorphous silicon film 4, and n-type amorphous silicon films 51 and 61 are formed using a device (on). In Figure 2(b), 1
01 is the load chamber, 102 is the gate insulating film deposition chamber,
1020 is a control unit for gate insulating film deposition conditions, 103 is a semiconductor film deposition chamber, 104 is an n-type semiconductor film deposition chamber, and 105 is an unload chamber. below,
An outline of the manufacturing process of the thin film transistor shown in FIG. 1 will be explained with reference to FIG. 2(a). (A) Step 2. A metal film such as a chromium (Cr) film is formed on an insulating substrate 1 such as a glass plate by sputtering or the like, and a gate electrode 2 pattern is formed by well-known photoetching. (B) Process: The substrate on which the gate electrode pattern is formed is
Load chamber 101 of the plasma CVD apparatus shown in Figure (b)
The substrate is set to 1, preheated, and the load chamber 101 is evacuated.Then, the substrate is transferred to the gate insulating film forming chamber 102 and filled with silane and nitrogen. A reactive gas such as ammonia is introduced, and the control unit controls the reactive gas composition and film-forming power. While changing the film forming conditions such as film forming gas pressure and film forming temperature,
A silicon nitride film to be used as the gate insulating film 3 is formed so as to satisfy the conditions shown in FIG. 1(b). In other words, the hydrogen content in the gate insulating film 3 can be controlled by, for example, changing the CVD source gas composition as the film thickness increases, and increasing the flow rate of ammonia relative to silane increases the hydrogen content. . Furthermore, if the temperature during CVD is controlled high, the hydrogen content can be reduced, and if the temperature is controlled low, it can be increased. (C) Step: The substrate on which the gate insulating film 3 has been formed is transferred to the semiconductor film forming chamber 103, and an amorphous silicon film is formed from silane and hydrogen. (D) Step: The substrate on which the amorphous silicon film has been formed is transferred to the n-type semiconductor film forming chamber 104, and an n-type amorphous silicon film is formed from silane, phosphine, and hydrogen. Thereafter, the substrate is cooled in the unload chamber 105 and then taken out. (E) Step: A silicon-based semiconductor film island pattern 4 made of an amorphous silicon film or the like is formed by a well-known photoresist process and dry etching. (F) Process 2 A gate insulating film 3 made of a silicon-based insulating thin film is formed by a well-known photoresist process and dry etching.
The gate electrode is selectively etched to expose the gate electrode. Note that this etched portion is not shown in FIG. (G) Process A metal film such as aluminum is formed by sputtering, and electrode patterns 52 and 62 made of the metal film are formed by a well-known photoetching process.Next, by well-known dry etching, n-type The amorphous silicon film is separated into 51 and 61, which are used as a drain electrode 5 and a source electrode 6. With the above steps, the thin film transistor shown in FIG. 1 is completed. The present invention is applied in that in step (B), the hydrogen content of the silicon nitride film is distributed in the film thickness direction to change the dry etching rate with the fluorine compound gas. The effects of the present invention will be explained below with reference to FIG. 3, which shows the connection between the drain bus line and the drain terminal at the etching step of the gate insulating film. Figure 3 shows the flow of the process, and in Figure 1,
1 is an insulating substrate, 3 is a gate insulating film, 9 is a drain bus line, 9' is a drain terminal, and 10 is a resist pattern. (A) process shows how the resist pattern 10 is formed for etching the gate insulating film 3, and (B) process shows the process of etching the gate insulating film 3 by dry etching using fluorine compound gas. (C) Step shows how etching is completed; (D) Step shows after the resist pattern 10 has been removed. A state in which the drain bus line 9 and the drain terminal 9 are connected through the etched step of the gate l//A edge film 3 is shown. When the gate insulating film is etched, the etched surface enters under the resist pattern 10 as shown by the arrow in step (B). By applying the present invention, the amount that the etched surface penetrates under the resist pattern 10 is limited to the upper layer of the gate insulating film 3 (the side closer to the resist pattern 10).
It gets bigger. As a result, etching was completed (C)
In the process, the etching step of the gate insulating film 3 is gradually tapered. Therefore, the connection between the drain bus line 9 and the drain terminal 9' at the etching step of the gate insulating film 3 can be made perfect. For example, the wiring width of the drain bus line 9 is lOII.
m, if the thickness of the thin film constituting the wiring is approximately the same as that of the silicon nitride film, and the etching step of the silicon nitride film is steep and nearly perpendicular, the wiring resistance will be Lo
It often exceeds okΩ, and sometimes breaks. Such problems can be solved by applying the present invention. A similar effect can be obtained when the source electrode 6 of the thin film transistor and the display pixel electrode 7 made of tin oxide or indium oxide are connected through the etched step 3' of the gate electrode 3, as shown in FIG. 5(b). It can also be seen in That is, although the silicon nitride film 3 on the display pixel electrode 7 in FIG. 5(b) is removed by dry etching using fluorine compound gas, by applying the present invention, the upper layer of the gate insulating film 3 Since the etching speed is higher than that of the lower layer, the etching step of the silicon nitride film is
As in the case of Figure (c), it can be made to have a gradual inclination with a forward taper. As a result, the reliability of the connection between the source electrode 6 and the display pixel electrode 7 can be significantly improved. For example, if the etching steps of the silicon nitride film are steep and nearly perpendicular as shown in FIG. 5(b), connection failures often occur, but these problems have been eliminated by application of the present invention. In this embodiment, a silicon nitride film is used as the gate insulating film 3, but in this case, the characteristics of the thin film transistor itself shown in FIG. 1 can also be improved, and favorable results can be obtained. To explain this in detail below, the silicon nitride film has a stoichiometric composition of 5xsN*
At (N/Si ratio=473), the etching rate is low and the film has a high withstand voltage (dielectric breakdown electric field). but,
When a silicon nitride film with a stoichiometric composition is formed by a plasma CVD method, etc., there are many Si dangling bonds (dangling bonds), and thin film transistors applied to pure gate edge films have poor stability against gate voltage stress. cannot be said to be good. Therefore, the composition of the gate insulating film 3 in the region in contact with the semiconductor film pattern 4 is set to N/Si≧
473 (often accompanied by increased hydrogen content) Si
It is necessary to reduce dangling bonds. That is, as the composition of the silicon nitride film used for the gate insulating film 3 approaches the semiconductor film pattern 4, increasing the composition N/Si ratio is effective for stabilizing the thin film transistor. The film quality change in the film thickness direction of this silicon nitride film is in the same direction as the present invention. In other words, by applying the present invention, it is possible to improve the reliability of electrode connections and wiring as well as the characteristics of the thin film transistor itself. The effect described above is that the film quality of the gate insulating film 3 changes in the film thickness direction, and the film becomes closer to the semiconductor film pattern 4 (upper layer).
This is caused by increasing the dry etching rate with the fluorine compound gas. In this example, a silicon nitride film is used as the gate insulating film, and the film quality such as its composition is changed. Oxygen is added to the silicon-based insulating thin film used as the gate insulating film, and the amount of oxygen is adjusted to The distance may be increased as the distance from the film thickness increases. In order to change the film quality of this silicon-based insulating thin film, it is possible to manually change the film-forming conditions, but as in the fifth embodiment, a control unit such as a minicomputer or a microcomputer can be used to form a silicon-based insulating thin film. It is effective to include it in the device. In addition, the gate insulating film 3 requires a certain thickness or more in order to guarantee electrical breakdown voltage, but in order to increase mass production,
There is no problem in sequentially forming films without breaking the vacuum in 2 to 4 separate film forming chambers arranged in series. Example 2 This example relates to an image display device consisting of a liquid crystal display device using the thin film transistor and active matrix circuit board shown in Example 1, and FIG. 4(a) is a plan view of the main part thereof. (b) shows a cross-sectional view. In the figure, 80 is the thin film transistor 8 shown in the construction drawing.
Connect the drain bus line 9 to the drain electrode 5 of 9,
An active matrix circuit board in which a gate bus line 8 is connected to the gate electrode 2 and a display pixel electrode 7 is connected to the source electrode 6, 20 is a polarizing plate, 21 is a color filter,
23 is a counter electrode of the display pixel electrode 7 made of a transparent conductive film, which is also made of a transparent conductive film; 22.26;
24 represents a protective film, 24 represents an alignment film, and 25 represents a liquid crystal filling the void. This example of the image display device has the above-described configuration and is for color display. Further, this display device can be easily manufactured using a manufacturing process similar to that of a well-known color liquid crystal display device. Note that in an actual display device, in addition to the configuration shown in FIG. 4, various electrical circuit control systems and illumination means from the back are provided as well-known image display movement means, but these are not shown in the figure. and the explanation has been omitted. Example 3 In this example, a multilayer gate insulator is used, in which the gate insulating film is composed of a plurality of films having different etching rates. An example of a thin film transistor having a film is shown. Therefore, the thin film transistor of this embodiment is basically the same as that of the first embodiment except for the structure of the gate insulating film. An embodiment of the present invention will be described below with reference to FIGS. 6 to 10. FIG. 6 shows a cross-sectional view of a thin film transistor to which the present invention is applied. In the figure, 1 is an insulating substrate such as a glass substrate, 2 is a gate electrode made of a metal film such as chromium, 31 is the 1Nth gate insulating film 3 made of a silicon-based insulating thin film, and 32 is a silicon-based insulating film. The second layer of the gate insulating film 3 is a thin film, 4 is a semiconductor film pattern made of an amorphous silicon film, and 51 and 61 are semiconductor films made of an n-type amorphous silicon film doped with phosphorus. 52 and 62 are metal films such as aluminum, 5 is a drain electrode, and 6 is a source electrode. The present invention is applied in that the gate insulating film 3 has a two-layer structure, and the dry etching rate using a fluorine compound gas is higher in the second layer than in the first layer. The manufacturing process of this thin film transistor will be explained below with reference to FIG. FIG. 7(a) shows plasmas C, VD (Ch.
(A) to (H) of the same figure (b) show the manufacturing process flow of the thin film transistor. (A) Process: Chromium (
A metal film such as a Cr) film is formed by sputtering or the like, and a pattern of the gate electrode 2 is formed by well-known photoetching. (B) Step: Set in the load chamber 101 of the plasma CVD apparatus shown in FIG. 7(a), preheat the sample 100,
The load chamber 101 is evacuated. Thereafter, the sample is transferred to the first film forming chamber 1021, and reactive gases of silane, nitrogen, and hydrogen are introduced, and the first film forming chamber 1021 is
A first M silicon-based insulating thin film 31 made of a silicon nitride film is formed as a layer. Note that this insulating thin film 31 contained hydrogen atoms at 1.5XIO°/d, and the N/Si atomic ratio was about 1.3. (C) Process: The sample 100 on which the first M silicon-based insulating thin film 31 has been deposited is transferred to the second film-forming chamber 1022, and reactive gases of silane, nitrogen, and hydrogen are introduced to form the second layer of the gate insulating film 3. A second N silicon-based insulating thin film 32 made of a silicon nitride film or the like is formed. In this case, the film forming conditions such as reaction gas composition and film forming power are changed to the first layer silicon-based 111! ! Edge thin film 3
Change it to case 1. The second layer silicon-based insulating thin film 32 is selected so as to have a higher etching rate than the first layer silicon-based insulating thin film 31. In this example, the insulating thin film 32 contains 2.5 x 10"/al of hydrogen atoms, and the N/Si atomic ratio is approximately 1.4. The etching rate is higher than that of the first insulating thin film 31. It was about 5 times faster.The practical etching rate difference between the first layer and the second layer insulating film is sufficient if it is 5 to 10%, and there is no need to make it extremely large. (D) Process : Transfer the sample on which the gate insulating film 3 has been formed to the third film forming chamber 103, and form an amorphous silicon film from silane and hydrogen. (E) Process: Sample on which an amorphous silicon film has been formed was transferred to the fourth film forming chamber 104, and silane, phosphine, hydrogen to n
A mold-shaped amorphous silicon film is deposited. Thereafter, the sample is cooled in the unloading chamber 105 and then taken out. (F) Step: A silicon-based semiconductor film island pattern 4 made of an amorphous silicon film or the like is formed by a well-known photoresist process and dry etching. (G) Process: A gate insulating film 3 made of a silicon-based edge thin film is formed by a well-known photoresist process and dry etching.
The gate electrode is etched and the terminal of the gate electrode is brought out.
This etched portion is not shown in FIG. (H) Process A metal film such as Ni aluminum is formed by sputtering, and electrode patterns 52 and 62 made of the metal film are formed by a well-known photoetching process. Then,
By well-known dry etching, the n-type amorphous silicon film on the channel is separated into 51 and 61, and the drain electrode 5 is separated.
and source electrode 6. With the above steps, the thin film transistor shown in FIG. 6 is completed. The steps to which the present invention is applied are (B) and (C). The effects of the present invention will be seen in FIGS. 8 to 10. Figure 8 shows
This is an example in which the thin film transistor shown in FIG. 6 is applied to an active matrix substrate, and a source electrode 6 and a display pixel electrode 7 made of tin oxide or indium oxide are connected through the etched step of the gate electrode 3. The display pixel electrode 7
The upper silicon nitride film is removed by dry etching using fluorine compound gas, but by applying the present invention,
Since the etching rate of the second layer 32 of the gate insulating film 3 is higher than that of the first layer 31, the etching step of the silicon nitride film can be made gentle as shown in the figure. As a result, sauce il! Pole 6 and display pixel Ml
As in the case of Example 1, the connection reliability of the electrodes can be significantly improved. For example, if the etching steps of the silicon nitride film are steep and nearly perpendicular, poor connections often occur, but these problems have been eliminated by application of the present invention. This becomes clearer in the case of the example shown in FIG. FIG. 9 shows a thin film transistor according to the present invention applied to an active matrix substrate, and an external connection terminal 9' of a drain bus line 9 existing on a gate insulating film 3 is connected to a gate electrode 2 on an insulating substrate 1 such as a glass substrate. This is an example in which the gate bus line 8 and the gate bus line 8 are arranged on the same plane. Note that each electrode and a group of electrodes such as wiring on the insulating substrate l are formed by the same process. The drain bus line 9 is clearly connected to the connection terminal 9' through the gradual etching step of the gate insulating film 3. The wiring width of this drain bus line 9 is 10. If the thickness of the thin film constituting the wiring is approximately the same as that of the silicon nitride film, and the etching step of the silicon nitride film is steep and nearly perpendicular as in the conventional case, the wiring resistance will be 100%. It often exceeds Ω, and sometimes leads to disconnection. However, in the case of FIG. 9, since the present invention is applied, the above-described problems of high wiring resistance and disconnection are eliminated. Such an effect of the present invention is obtained when the gate insulating film 3 is
This is caused by increasing the etching speed on the upper layer (second layer) side when etching the ftI structure. A similar effect can be obtained by making the gate insulating film 3 multilayered with three or more layers and increasing the etching rate in the upper layer, but considering the equipment investment for mass production, etc.
It is appropriate to have four layers. Further, in order to keep the interface state between each layer constituting the gate insulating film 3 clean, it is desirable to continuously form the films without breaking the vacuum. And Gate II! If the film forming chambers for each layer constituting the III film 3 are separated and arranged in series as in this embodiment, productivity can be improved. Further, according to the present invention, the characteristics of the amorphous silicon thin film transistor itself can be improved, and defects such as clouding of the amorphous silicon film, which is a semiconductor film, can be prevented. This will be explained with reference to FIG. FIG. 10(a) is a characteristic curve diagram illustrating the effects of the present invention, showing the relationship between the effective mobility and threshold voltage variation of a thin film transistor and the total thickness of the gate insulating film 3. This shows the relationship with the value. Also, the first
FIG. 0(b) is a curve diagram showing the principle. Figure 10 (
b) The etching rate depends on the reaction gas composition (ammonia/silane gas introduction ratio) and its fluorine compound gas (for example, methane tetrafluoride, sulfur hexafluoride, etc.) when forming a silicon nitride film, and the gate stitching rate. This figure shows the relationship between the effective mobility of an amorphous silicon thin film transistor used as an edge film and the amount of variation in threshold voltage due to gate voltage stress. In the plasma CVD apparatus used by the inventors for the study, even if the ammonia/silane gas introduction ratio is O, the nitrogen/silane gas in the reaction gas is adjusted so that the N/Si ratio of the silicon nitride film is 1.3 or more. Increase the introduction ratio to 1
5. Film forming power (frequency: 13.56MHz) is 500W
The reaction gas pressure was 79.8 Pa, and the film forming temperature was 300°C. As the ammonia/silane gas introduction ratio increases, the hydrogen and nitrogen contents of the silicon nitride film to be formed increase, resulting in a lower density of the film and an increase in the dry etching rate of the silicon nitride film. Furthermore, as the ammonia/silane gas introduction ratio increases, the dangling bonds of silicon in the silicon nitride film decrease, so that the threshold due to gate voltage stress of an amorphous silicon thin film transistor using a silicon nitride film as a gate insulating film decreases. Although the value voltage shift can be reduced, amorphous silicon film/silicon nitride film (an amorphous silicon film is laminated on a silicon nitride film)
Stress is added to the inside, and the effective mobility decreases. 10th
Figure (a) shows that in the thin film transistor shown in Figure 6, a silicon nitride film is applied to the first layer 31 of the gate insulating film 3, which has a low dry etching rate but increases the effective mobility, and the second layer 32, the dry etching speed is high, and the effective mobility of a thin film transistor using a silicon nitride film that suppresses the threshold voltage shift due to gate voltage stress, the amount of threshold voltage fluctuation due to gate voltage stress, and the silicon nitride of the I layer It shows the relationship between the relative film thicknesses of the film 31 (assuming the thickness of the gate insulating film is 1). Clearly, the features of the first R stitch 31 and the second R stitch 32 are utilized. In particular, it is found that it is effective when the relative thickness of the first silicon nitride film 3 is set to 0.2 to 0.8. It is also easy to see that inclined etching of the gate insulating film is possible. In addition, the amorphous silicon film used as the semiconductor film of the amorphous silicon thin film transistor has a large compressive stress (5×1
Therefore, depending on the stress of the gate insulating film, if the total stress of the semiconductor film/gate pure edge film increases toward the compressive side, it becomes more likely to become cloudy. In the example shown, the first layer 31 of the gate insulating film 3
Since the silicon nitride film forming the second layer 32 has compressive stress and the silicon nitride film forming the second layer 32 has tensile stress, by adjusting the thickness of the first R layer 31 and the second layer 32, the gate This means that the total stress of the insulating film can be adjusted. Therefore, by adjusting the total stress of the semiconductor film/gate insulating film, it is possible to prevent defects such as clouding of the amorphous silicon film constituting the semiconductor 1plJ4. The effects described above are produced by forming the gate insulating film 3 into a 2M structure and by satisfying certain film quality conditions for each layer. In the example described above, the gate insulating film 3 is made of 2N, but it may be made of more than 2N layers. However, considering efficiency and capital investment in mass production, it is appropriate to have 2 to 4 layers as described above. In addition, in the above example, each layer constituting the gate insulating film 3 is a silicon nitride film, and the film quality of the first layer 3 and the second R layer 32 is determined by the film formation conditions (in the above example, the reactive gas composition is taken up). However, one reaction gas introduction amount, one reaction gas pressure, film-forming power, power frequency, film-forming temperature, etc.)
It was changed by changing the . However, in order to achieve the same effect of the present invention, it is necessary to make the gate insulating film 3 41 and the lower insulating film (for example, 31) a silicon oxide film, or to Alternatively, a silicon nitride film with a large amount of oxygen added may be used. Incidentally, using the thin film transistor of Example 3 having the gate insulating film 3 made of this multilayer insulating film, an active matrix circuit board and an image display device using the same as shown in FIG. 4 were assembled in the same manner as in Example 2. A device having characteristics similar to those of Example 2 could be obtained. Effects of the Invention According to the present invention, the etching rate of the layer in contact with the semiconductor film of the gate insulating film is made higher than that of the lower layer, and the amount of side etching in the upper layer can be increased. Inclined etching is possible. Therefore, in active matrix circuit boards and image display devices using such thin film transistors, the reliability of the connection between the source electrode of the thin film transistor and the display pixel electrode through the etching step of the gate insulating film increases, and the reliability of the connection between the source electrode of the thin film transistor and the display pixel electrode through the etching step of the gate insulating film increases. This has the effect of preventing increases in wiring resistance and disconnection accidents.

[Brief explanation of drawings]

FIG. 1(a) is a cross-sectional structural diagram of a thin film transistor according to an embodiment of the present invention, and FIG. 1(b) is a curve diagram explaining the properties of the gate insulating film of the thin film transistor shown in FIG. 1(a).
FIG. 2(a) is a manufacturing process diagram of the thin film transistor shown in FIG. 1(a), FIG. 2(b) is a block diagram of a manufacturing apparatus showing an embodiment of the manufacturing method according to the present invention, and FIG.
4(a) and 4(b) are a plan view and a sectional view, respectively, showing an embodiment of an image display device according to the present invention, and FIG.
Figures (a), (b), and (c) are cross-sectional views of a conventional thin film transistor and active matrix circuit board, Figure 6 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention, and Figure 7 (a). FIG. 7(b) is a schematic diagram of a manufacturing apparatus as an embodiment for manufacturing the thin film transistor of the present invention.
7(a) is a manufacturing process diagram of the thin film transistor of the present invention using the apparatus shown in FIG.
10(a) is a characteristic curve diagram showing the effect of the thin film transistor of the present invention, and FIG. 10(b) is a characteristic curve diagram explaining the principle thereof. [Explanation of symbols 1 1... Insulating substrate 2... Gate electrode 3...
- Gate insulating film 3'...Etched step portion of gate insulating film 4...Semiconductor film 5...Drain electrode 6...Source electrode 7...Display pixel electrode 8...Gate bus line 9- ...Drain bus line 9'...Drain terminal 51.61...N-type semiconductor film 52.62...Metal film 20...Polarizing plate 21...
・Color filter 22.26...Protective film 23...
Counter electrode 24...Alignment film 25...Liquid crystal 31...First layer gate insulating film 32...Second layer gate insulating film 80...Active matrix circuit board 89...Thin film transistor 101 Load chamber 102.1021.1022 Gate insulating film deposition chamber 1020 Gate insulating film deposition chamber control unit 1
03... Semiconductor film deposition chamber 104... N-type semiconductor film deposition chamber 105... Unload chamber 107... Cathode electrode 108... High frequency power supply

Claims (1)

[Claims] 1. An electrode group comprising gate electrodes and other wiring and electrodes provided separately on an insulating substrate, and a gate formed to cover the electrode group. an insulating film;
a semiconductor film pattern disposed so as to be located on at least the gate insulating film on the gate electrode; and a drain electrode and a source electrode disposed at both ends of the semiconductor film pattern so as to overlap with at least the gate electrode. , at least one of the drain electrode and the source electrode and the other wiring electrode are electrically connected to a wiring conductor that is electrically connected to at least one of the drain electrode and the source electrode through an opening provided in the gate insulating film. In the thin film transistor, the gate insulating film is substantially connected to a wiring conductor that is connected to the wiring conductor and is present on an etched step provided in the gate insulating film, and the gate insulating film is substantially The gate insulating film is composed of a gate insulating film whose etching rate gradually decreases, and a step or an inclined part is provided on the wall surface of the opening provided in the gate insulating film, so that the slope of the wall surface of the opening is substantially gentle. thin film transistor. 2. The gate insulating film is composed of a silicon-based insulating thin film, and hydrogen or oxygen is contained in the gate insulating film, and in the case of hydrogen, the content is large on the surface side of the insulating film and gradually decreases in the depth direction. 2. The thin film transistor according to claim 1, wherein the thin film transistor has a concentration gradient, and in the case of oxygen, the content thereof is small on the surface side of the insulating film and gradually increases in the depth direction. 3. The gate insulating film has a multilayer structure with different etching rates, and the outermost insulating thin film in contact with the semiconductor pattern is a thin film with a high etching rate, gradually increasing as it moves away from the substrate in the internal depth direction. 2. The thin film transistor according to claim 1, comprising a laminated structure of thin films having a low etching rate. 4. When manufacturing the thin film transistor according to claim 1, 2 or 3, after forming an electrode group pattern having a gate electrode and other wiring electrodes on an insulating substrate, a gate is formed so as to cover the electrode group. The process of forming an insulating film includes a step of forming a film while sequentially moving within a plurality of insulating thin film forming chambers arranged in series from a thin film with a small etching rate to a thin film with a large etching rate without breaking the vacuum. After forming the semiconductor pattern, an electrode extraction hole is provided in the gate insulating film by dry etching with a fluorine compound gas using a predetermined resist mask pattern,
A step of exposing a part of the electrode group provided on the insulating substrate, and providing a drain electrode and a source electrode at both ends of the thin film semiconductor pattern at a distance from each other, and allowing the drain electrode to pass through the electrode lead-out hole on the substrate. A method for manufacturing a thin film transistor, comprising a step of forming a connection to a wiring electrode. 5. A plurality of thin film transistors according to claim 1, 2 or 3 are arranged in a matrix on the same insulating substrate, the gate electrodes of each thin film transistor are connected to form a first bus line, and the drain electrode is connected to the gate electrode. A matrix circuit board that connects to wiring electrodes provided on the insulating substrate through electrode extraction holes provided in the insulating film to form a second bus line. 6. Disposing a group of display pixel electrodes between the thin film transistors provided on the matrix circuit board according to claim 5, and
Each electrode terminal of this display pixel electrode group is connected to the source electrode of the corresponding thin film transistor, and furthermore, a counter electrode is provided opposite to the display pixel electrode group, and a counter electrode is provided in the gap between the display pixel electrode group and the counter electrode. An image display device consisting of a display cell filled with liquid crystal and sealed.