JPH0337699U - - Google Patents
Info
- Publication number
- JPH0337699U JPH0337699U JP9522389U JP9522389U JPH0337699U JP H0337699 U JPH0337699 U JP H0337699U JP 9522389 U JP9522389 U JP 9522389U JP 9522389 U JP9522389 U JP 9522389U JP H0337699 U JPH0337699 U JP H0337699U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- sense circuit
- memory device
- sense
- output buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 230000004044 response Effects 0.000 claims 1
Landscapes
- Static Random-Access Memory (AREA)
Description
第１図は本考案メモリ装置の回路図、第２図は
従来のメモリ装置の回路図である。
１……メモリセルブロツク、２……センスアン
プ、３……出力バツフア、１０……ノイズ低減回
路、１１……アナログスイツチ、１２……インバ
ータ。
FIG. 1 is a circuit diagram of a memory device of the present invention, and FIG. 2 is a circuit diagram of a conventional memory device. 1... Memory cell block, 2... Sense amplifier, 3... Output buffer, 10... Noise reduction circuit, 11... Analog switch, 12... Inverter.
Claims (1)
セルに接続されるビツト線と、 このビツト線の電位変動を検知して上記メモリ
セルに記憶された情報を判定するセンス回路と、 このセンス回路の判定結果を受けて外部負荷を
駆動する出力バツフア回路と、 を備えた半導体メモリ装置に於いて、 上記センス回路と上記出力バツフア回路との間
に、アドレス情報の変化タイミングに従つて開閉
制御されるスイツチ回路及び上記センス回路の出
力をラツチするラツチ回路からなるノイズ低減手
段を設けたことを特徴とする半導体メモリ装置。[Claims for Utility Model Registration] A plurality of memory cells arranged in rows and columns; a bit line connected to a specific memory cell selected according to address information; A semiconductor memory device comprising: a sense circuit that determines information stored in a cell; and an output buffer circuit that drives an external load in response to a determination result of the sense circuit, the sense circuit and the output buffer circuit 1. A semiconductor memory device characterized in that a noise reduction means is provided between the switch circuit and the switch circuit, which is controlled to open and close according to the change timing of address information, and a latch circuit that latches the output of the sense circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9522389U JPH0337699U (en) | 1989-08-10 | 1989-08-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9522389U JPH0337699U (en) | 1989-08-10 | 1989-08-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0337699U true JPH0337699U (en) | 1991-04-11 |
Family
ID=31644500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9522389U Pending JPH0337699U (en) | 1989-08-10 | 1989-08-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0337699U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6032917A (en) * | 1983-08-04 | 1985-02-20 | Mitsubishi Heavy Ind Ltd | Cylinder lubrication device |
| JPS61258396A (en) * | 1985-05-13 | 1986-11-15 | Seiko Epson Corp | Semiconductor memory circuit |
-
1989
- 1989-08-10 JP JP9522389U patent/JPH0337699U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6032917A (en) * | 1983-08-04 | 1985-02-20 | Mitsubishi Heavy Ind Ltd | Cylinder lubrication device |
| JPS61258396A (en) * | 1985-05-13 | 1986-11-15 | Seiko Epson Corp | Semiconductor memory circuit |