JPH0341003B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a circuit for absorbing high frequency surge voltage, and particularly to a surge absorption circuit suitable for semiconductor integrated circuits.

[Prior art]

Many of the input signals in automotive electronic systems originate from mechanical contacts.

When such a mechanical switch is turned off, a high frequency surge voltage is generated due to the combination of wiring inductance and stray capacitance.

For example, as shown in Figure 4, the above surge voltage has a peak voltage of about ±300V and a frequency of 1MHz.
A substance with a half-life of about 10 μs is produced.

CMOS for high frequency surges such as those mentioned above
As a surge protection circuit for an integrated circuit, there is one described in, for example, Japanese Patent Laid-Open No. 110553/1983.

FIG. 5 is a circuit diagram of an example of the above surge protection circuit.

In FIG. 5, a filter consisting of a resistor 2 and a capacitor 3 is connected between the input terminal 1 and the input terminal 5 of the integrated circuit 4, and the filter is configured to absorb surges. There is.

[Problem that the invention seeks to solve]

In the circuit shown in Fig. 5 above, if the peak voltage of the surge is V _P , the input threshold voltage of the CMOS circuit is V _th , the frequency of the surge is f, the resistance value of resistor 2 is R, and the capacitance of capacitor 3 is C , below (1)
The formula holds true.

V _P /V _th ≒2πfCR ...(1) In the above equation (1), V _P = 300V, V _th = 6V, f
= 1 MHz and R = 100 kΩ, it can be seen that the capacitance C of the capacitor 3 should be 80 pF or more.

However, incorporating a capacitance as large as 80pF inside an integrated circuit is not practical as it would occupy a very large area.

For example, in order to form a capacitance of 80 pF with a gate oxide film, a size of 0.5×0.5 mm is required, which results in a very large area occupied inside the integrated circuit.

Therefore, the resistor 2 and capacitor 3 shown in FIG. 5 must be provided as separate components outside the integrated circuit, which poses problems in terms of cost and miniaturization.

Note that in the above circuit, if the value R of the resistor 2 is increased, the capacitance C of the capacitor 3 can be reduced, but if R is increased, the input impedance increases and there is a risk of malfunction.
Practically speaking, the above-mentioned value of about 100 kΩ is appropriate.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a surge absorption circuit in which a capacitor can be housed inside an integrated circuit.

[Means to solve the problem]

In order to achieve the above object, in the present invention,
By connecting a capacitor between the input and output terminals of the inverting amplifier circuit inside the integrated circuit and increasing the apparent capacitance using the Miller effect, it is configured to form an effective surge absorption circuit in a small area. are doing.

[Embodiments of the invention]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In FIG. 1, resistor 2 is connected between input terminal 1 and input terminal 5 of integrated circuit 4. In FIG.

Note that this resistor 2 can also be formed inside the integrated circuit 4, as described later.

Further, within the integrated circuit 4, a voltage clamp circuit 6 is formed as a countermeasure against static electricity of the gate electrode in the CMOS structure.

This voltage clamp circuit 6 has p ⁺ diffusion resistance 6a
and a diode 6b formed of a p-well and an n ⁺ diffusion layer formed within the p-well.

The output end of this voltage clamp circuit 6, ie, point B, is connected to the input end of CMOS inverter 8, ie, point C, via a resistor 7.

Further, as the resistor 7, a polysilicon resistor or a diffused resistor formed within the integrated circuit 4 can be used.

CMOS inverter 8 is p-channel CMOS
It is composed of a transistor _T11 and an n-channel CMOS transistor _T12 , and a capacitor 9 that generates a mirror effect is connected between the input terminal point C and the output terminal point D.

Figure 2 shows a CMOS including the above capacitor 9.
1 is a cross-sectional view of one embodiment of an integrated circuit of an inverter 8. FIG.

In FIG. 2, 11 is an n-type silicon substrate;
2 is a p-well layer, 13 and 14 are gate oxide films,
15 and 16 are gate electrodes, 17 and 18 are p ⁺ layers,
19 and 20 are n ⁺ layers, 21 is a field oxide film,
22 is an Al wiring.

and p by 13, 15, 17 and 18
A channel CMOS transistor T ₁₁ is formed, and 14, 16, 19 and 20 form an n-channel CMOS transistor T ₁₂ .

Also, gate electrode 1 of CMOS transistor _T12
6 and the n ⁺ layer (drain diffusion layer) 19 constitute a capacitor 9, which partially overlaps with the CMOS transistor _T12 .

Next, FIG. 3 is a diagram of voltage waveforms of the circuit of FIG. 1, and A to D indicate voltage waveforms at locations denoted by the same reference numerals in FIG. 1, respectively.

Hereinafter, the operation of the circuit shown in FIG. 1 will be explained based on FIG. 3.

When a high frequency surge as shown in FIG. 3A is input to the input terminal 1, it is clamped to the current voltage V _d or the ground voltage (OV) by the voltage clamp circuit 6, so the voltage waveform at point B is as shown in FIG. 3. It becomes as shown in B.

Note that the resistor 2 has a value of about several tens of kΩ, and limits the clamp current flowing to the diode 6b due to a surge.

Next, the voltage at point B clamped as described above is integrated by a CR integration circuit including a resistor 7 and a capacitor 9, resulting in an integrated waveform as shown in FIG. 3C.

Note that the waveform in FIG. 3C shows the resistance value of resistor 7.
100kΩ, capacitance of capacitor 9 1pF, CMOS
Let the channel width W and channel length L of the p-channel transistor _T11 of the inverter 8 be W/L=
300/40, and a simulation result when the channel width and channel length of the n-channel transistor _T12 are set as W/L=150/40.

As can be seen from FIG. 3C, the voltage at the input terminal of the CMOS inverter 8, that is, at point C, does not exceed the threshold voltage V _d /2, so the waveform at point D is as shown in FIG. 3D. It can be seen that the power supply voltage V _d is maintained and high frequency surges are absorbed.

As described above, in the circuit shown in FIG. 1, the capacitance of the capacitor 9 of about 1 pF can sufficiently absorb high frequency surges.

As mentioned above, the reason why high frequency surges can be absorbed using a capacitor with a much smaller capacitance than before is as follows.

In other words, if a capacitor 9 is connected between the input and output ends of an amplifier circuit where the input and output have opposite polarities, such as the CMOS inverter 8 in FIG.
The capacitance of this capacitor increases by 1-A due to the Miller effect when viewed from the input side. Furthermore, A is
This is the amplification degree of the CMOS inverter 8, and - indicates that the polarity is opposite. Therefore, the capacitance of the capacitor 9 is amplified using the CMOS inverter 8. Therefore, the time constant of the CR integrating circuit consisting of resistor 7 and capacitor 9 as seen from the input side becomes larger than the actual value, so high frequency surges can be sufficiently absorbed using a small capacitor.

In the configuration shown in FIG. 2, in order to form a capacitance of 1 pF, the thickness of the gate oxide film 14 must be 1000 Å.
In this case, the occupied area is 2800 μm ² .

Therefore, it is possible to form it in an extremely small area of about 50 μm square.

In addition, in Fig. 2, the n-channel
The case where the capacitor 9 is formed by overlapping the drain diffusion layer and the gate electrode of a CMOS transistor is illustrated, but the p-channel CMOS
The same effect can be obtained even if the transistor _T11 is formed by overlapping the drain diffusion layer and the gate electrode.

Furthermore, if the time constants of the resistor 2 and capacitor 9 are made large, high frequency surges can be absorbed even if the resistor 7 is omitted.

In addition, in FIG. 2, the integrated circuit 4 of the resistor 2
Although shown is a case in which it is provided outside the integrated circuit 4, it is also possible to form it inside the integrated circuit 4 using a polysilicon resistor or the like, and it is also possible to eliminate individual components around the integrated circuit.

Next, FIG. 6 is a diagram showing a second embodiment of the present invention,
A case is shown in which a Zener diode 10 is used as a voltage clamp circuit.

If the configuration is as shown in FIG. 6, no current will flow into the n-type silicon substrate (potential is _Vd ), thereby eliminating the possibility of latch-up.

Note that the Zener diode can be realized by a pn junction formed in a p-well.

In that case, by setting the zener voltage slightly higher than the threshold voltage of the CMOS inverter 8 (usually 1/2 of the power supply voltage V _d ), the charging time of the integrating circuit consisting of the resistor 7 and capacitor 9 can be lengthened. Therefore, the surge absorption effect can be enhanced and the capacitance of the capacitor 9 can be further reduced.

For example, if the power supply voltage is 12V, set the Zener voltage to
In order to set the voltage to 8V, the p ⁺ surface concentration at the pn junction should be approximately 1×10 ¹⁸ /cm ³ .

Next, FIG. 7 shows a third embodiment of the present invention.

This embodiment is an example in which a Schmitt trigger circuit 11 is used instead of the CMOS inverter 8.

When a Schmitt trigger circuit is used, the charging and discharging time of the integrating circuit made up of the resistor 7 and the capacitor 9 can be increased, so that the surge absorption effect can be enhanced. Therefore, the capacitance of the capacitor 9 can be further reduced.

An example of design values for each of the transistors T ₁ to T ₁₀ constituting the Schmitt trigger circuit 11 is shown below.

Channel width (μm) Channel length (μm) T ₁ 24 15 T ₂ 17 7 T ₃ 19 7 T 4 19 7 T ₅ 14 7 T _{6 14} 6 T ₇ 17 6 T ₈ 24 7 T ₉ 24 7 T ₁₀ 24 13 [Effects of the Invention] As explained above, in the present invention, a resistor, a voltage clamp circuit connected to one end of the resistor, an inverting amplifier circuit connected to the output end of the voltage clamp circuit, and a Since the structure includes a feedback capacitor connected between the input terminal and the output terminal of the inverting circuit, the apparent value of the feedback capacitance can be increased due to the Miller effect. It is possible to sufficiently absorb high-frequency surges using a capacitor with a capacitance value (about 1 pF) that poses no practical problems when forming a capacitor.

Therefore, there is no need to provide an independent capacitor outside the integrated circuit, which results in lower costs and the ability to downsize the device. Note that since it is easy to provide a resistor inside an integrated circuit, the present invention allows the entire surge absorption circuit to be provided inside an integrated circuit.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a sectional view of an embodiment of the integrated circuit of the invention, Fig. 3 is a voltage waveform diagram of the circuit of Fig. 1, and Fig. 4 is a surge voltage waveform diagram of the circuit of Fig. 1. Voltage waveform diagrams, FIG. 5 is an example of a conventional example, and FIGS. 6 and 7 are diagrams of other embodiments of the present invention. Explanation of symbols, 1...Input terminal, 2...Resistance, 3
...Capacitor, 4...Integrated circuit, 5...Input terminal of integrated circuit, 6...Voltage clamp circuit, 6a...
... p ⁺ diffused resistor, 6b ... diode, 7 ... resistor, 8 ... CMOS inverter, 9 ... capacitor, 11 ... n-type silicon substrate, 12 ... p well layer, 13, 14 ... gate oxide film , 15, 16
...gate electrode, 17, 18...p ⁺ layer, 19,
20...n ⁺ layer, 21...field oxide film, 2
2...Al wiring.

Claims (1)

[Claims] 1: a first resistor; connected to one end of the first resistor;
a voltage clamp circuit that limits the input surge power supply voltage or ground voltage through a resistor; and a second voltage clamp circuit connected to the output terminal of the voltage clamp circuit.
an inverting amplifier circuit connected to the other end of the second resistor for amplifying and inverting the input signal and outputting the inverted signal; and a feedback circuit connected between the input terminal and the output terminal of the inverting amplifier circuit. A surge absorption circuit comprising: a capacitor, and absorbs a surge input to the other end of the first resistor.