JPH0341352U - - Google Patents

Info

Publication number
JPH0341352U
JPH0341352U JP10015489U JP10015489U JPH0341352U JP H0341352 U JPH0341352 U JP H0341352U JP 10015489 U JP10015489 U JP 10015489U JP 10015489 U JP10015489 U JP 10015489U JP H0341352 U JPH0341352 U JP H0341352U
Authority
JP
Japan
Prior art keywords
identification number
host computer
control device
channel control
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10015489U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10015489U priority Critical patent/JPH0341352U/ja
Publication of JPH0341352U publication Critical patent/JPH0341352U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案を実施したＩ／Ｏチヤネル制御
装置の構成図、第２図は本考案装置においてホス
ト・コンピユータから与えられるインターフエイ
ス情報の内容を表わす図、第３図はＩ／Ｏチヤネ
ル制御装置を用いたシステムの全体を表わす図、
第４図は第３図に示すシステムのソフトウエア概
念図である。 １……ホスト・コンピユータ、２……メモリ、
３……Ｉ／Ｏチヤネル制御装置、３１……ホスト
・コンピユータ・インターフエイス、３２……マ
イクロプロセツサ、３３……内部メモリ、３４…
…ＳＣＳＩバス・インターフエイス、４……ＳＣ
ＳＩバス、５……二重化デイスク装置、５１，５
２……磁気デイスク、６……テープ装置、ＳＢ…
…システム・バス。 Figure 1 is a block diagram of an I/O channel control device implementing the present invention, Figure 2 is a diagram showing the contents of interface information given from a host computer in the device of the present invention, and Figure 3 is an I/O channel diagram. A diagram showing the entire system using a control device,
FIG. 4 is a conceptual software diagram of the system shown in FIG. 3. 1...Host computer, 2...Memory,
3...I/O channel control device, 31...Host computer interface, 32...Microprocessor, 33...Internal memory, 34...
...SCSI bus interface, 4...SC
SI bus, 5... Duplex disk device, 51,5
2...Magnetic disk, 6...Tape device, SB...
...system bus.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] システム・バスを介してホスト・コンピユータ
に接続されるとともに、少なくとも二重化デイス
ク装置及びその他のＩ／Ｏ装置等のデバイスを接
続するＩ／Ｏチヤネル制御装置において、前記ホ
スト・コンピユータからアクセス識別番号が設定
されるインターフエイス情報を送出するようにし
、前記アクセス識別番号を登録する登録手段と、
この登録手段内に設定された値とその後与えられ
たインターフエイス情報内の識別番号との一致を
判定する判定手段と、この判定手段から不一致信
号が出力された場合にこのインターフエイス情報
に対応する処理要求を待ち行列として格納するメ
モリ手段とを設けたＩ／Ｏチヤネル制御装置。 An access identification number is set by the host computer in an I/O channel control device that is connected to a host computer via a system bus and connects at least devices such as a duplex disk device and other I/O devices. registration means for transmitting interface information to be accessed and registering the access identification number;
a determination means for determining whether the value set in the registration means matches an identification number in the interface information given afterward; An I/O channel control device comprising memory means for storing processing requests as a queue.
JP10015489U 1989-08-28 1989-08-28 Pending JPH0341352U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10015489U JPH0341352U (en) 1989-08-28 1989-08-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10015489U JPH0341352U (en) 1989-08-28 1989-08-28

Publications (1)

Publication Number Publication Date
JPH0341352U true JPH0341352U (en) 1991-04-19

Family

ID=31649174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10015489U Pending JPH0341352U (en) 1989-08-28 1989-08-28

Country Status (1)

Country Link
JP (1) JPH0341352U (en)

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