JPH0341959B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to a light control device for use on a stage or in a studio. BACKGROUND TECHNOLOGY A light control device is a device that realizes the illumination levels of multiple lighting loads set by an operation unit and realizes mutual transition of scenes (scenes) that are a collection of illumination levels of multiple lighting loads. , it is necessary to realize operations on the operating unit faithfully, smoothly, and without time delay. In recent years, lighting loads or dimmer units that are controlled by a single dimmer (devices that control the lighting level of the lighting load by controlling the phase of the power supply voltage to the lighting load based on the dimming signal from the dimmer) The number of devices is increasing, and the problem has become how to process dimming calculations quickly and realize a device with good response. As a conventional example, there is a light control device 21 that utilizes the hardware configuration of a normal computer as it is. The configuration and operation of the calculation section of such a light control device 21 will be explained with reference to FIG. 8. In the light control device 21, the memory 22 in which the illumination level Ai for each channel (synonymous with the light control unit) of scene A is stored can store level data for the number of channels, and can be adjusted by inputting to the address signal terminal AD. One channel (i) is selected and by activating the output control input terminal OE,
Level data Ai is output from the data output terminal DT. The memory 23, which stores the illumination level Bi for each channel of scene B, stores other data in the same format as the memory 22. In the memory 24 in which the progress value of the fade is stored, there is no address input because the data is single. Similarly, data is output when the terminal OE input becomes active. The output unit 25 holds an output level that is a calculation result for each channel. When channel (i) is selected by the input to the address signal terminal AD and the write control input terminal WE becomes active, the data given to the data input terminal DT at that time is captured and held. An arithmetic unit (ALU) 26 performs basic operations such as addition, logical sum, and logical product. A pair of data to be calculated is input to the terminals x and y, and is taken in by signals to the write control input terminals I1 and I2, respectively. The terminal z is a data output terminal for the calculation result, for example x+y. Terminal 3 is an input terminal for the output control signal of terminal z. For convenience of data processing, the memory 27 for temporarily storing data includes input terminals for address input terminal AD, data input terminal DT, write control input WE,
It has an input terminal for a read control input terminal OE. Terminals O1 to O9 of decoder 28 are output terminals. An address signal from a read-only memory (ROM), which will be described later, is applied to the input terminal AD. For example, AD of memories 22, 23 and output section 25
8 bits AD0 to AD7 are applied to the input, 2 bits AD8 to AD9 are applied to the AD input of the memory 27, and 3 bits AD10 to AD12 are applied to the decoder 28. ST input is 2 bits ST0 to ST1 and is decoded as shown in the table below. Depending on the decoded data, various operations as shown in Table 1 are performed. For example, 24→27 means reading from memory 24 to memory 27.

[Table] A ROM (read only memory) 29 is provided in which a program for controlling processes for calculation is stored. AD is an address input terminal, and DT is a data output terminal. Data from a program counter 30 that increases one by one is input to the address input. Its output is determined by the data content of ROM29. The data output of the ROM 29 is sent to the decoder 28 and memories 22, 23, 27 as the aforementioned A0 to A10 and ST0, ST1.
The signal is applied to the output section 25. A counter 30 and an oscillator 31 are provided. The output of oscillator 31 is applied to clock input terminal CK of counter 30. Data input/output terminal DT of memories 22 to 24, output section 25 and memory 27
The terminals x, y, and z of the arithmetic unit 26 are data input or output terminals, respectively, and are all connected by the same data line 32. In this configuration, the fade calculation is performed by programming the ROM 29 so as to follow the flowchart shown in FIG. In step n1 of FIG. 12, illumination data Ai for one channel (i) is read from the memory 22,
Further, in step n2, illumination data Ai of the scene to be reached is read out starting from the illumination data Bi.
Next, fade progress data F indicating the degree of progress of the fade operation is transferred from the memory 24 to step n.
Read at step 3. Next, in step n4, the arithmetic unit 26 performs the following calculation: Oi=Bi+F(Ai-Bi) (1). At step n5, the calculation result Oi of the first equation is stored at the corresponding address in the memory 27. Next, the channel number i at this point is incremented by +1, that is, the processing consisting of steps n1 to n5 as described above for channel number (i+1) is performed. In this way, calculations are performed for the number of channels. In this conventional example, many steps are required to perform the fade calculation for one channel. Not limited to this conventional example, if the computer configuration is used as is, the data line of each element is common, so the data exchange route can be set in any way depending on the program, and it is versatile. , data must be exchanged on a time-sharing basis, which increases the number of processing steps.
Even if a multiplier is provided as the arithmetic unit 26,
It is known that arithmetic processing for one channel takes at least seven steps. Since there is a certain limit to the time for one step due to the response speed of each component, this calculation time is proportional to the number of steps required for the fade calculation. In this light control device 21, the light control calculation is performed under the control of time-divided control sections, so the calculation time is long. In fact, this light control device 21 requires a configuration that has a circuit dedicated to light control calculations with a control unit (CPU, not shown) for light control calculations for every several dozen light control units, making the entire device large. It's getting complicated. Next, the illumination level as the fade progresses will be explained. For each dimmer unit, if the illumination levels of that dimmer unit in two scenes A and B are Ad and Bd, respectively, then the change in the illumination level of that dimmer unit due to a fade from scene B to scene A is linear. is ideal. In other words, it is a straight line consisting of slope (Ad-Bd) and intercept Bd, and is expressed as Bd+F(Ad-Bd)...(2). In stage lighting, etc., in addition to the changes in the illumination level related to each of the dimming units described above, it is also necessary to consider changes in the illumination level combined on the stage (referred to as photosynthesis) with respect to a plurality of dimming units. For example, a dimmer unit has a lighting load of red light,
On the other hand, assume that a lighting load of green light is connected to the dimmer unit. If the red lighting load is lit in scene A and the green lighting load is lit at the same level in scene B, the fade from scene B to scene A will cause the stage to change from green to green. and to red through the intermediate color of red,
Ideally, the transition should occur without any change in the lighting level. Taking into account the characteristics of the dimming unit, the characteristics of the load, and the characteristics of the eye, a control called up-down fade has recently been devised in order to smooth out the above two types of illumination level changes that occur simultaneously due to fade. It has been served. The light control calculation of the light control device 21 of the second conventional example can control this up-down fade. In other words, it is configured to have a memory that stores the fade progress value for up fade and a memory that stores the fade progress value for down fade, and after reading the illumination data Ai and Bi, compares the two and determines Ai. If >Bi, the up fade memory is read, and if Ai<Bi, the down fade memory is read. At this time, lighting data is used to control the up-down fade.
Several steps are required to compare Ai and Bi, which increases the calculation time. Purpose The purpose of the present invention is to solve the above-mentioned technical problems,
An object of the present invention is to provide a light control device that can significantly speed up fade calculation. Configuration of the Invention The configuration of the present invention for realizing the above object is to output illumination level data at the start of the fade for each channel of the lighting load, illumination level data after the end of the fade, and fade progress data for each channel. a control means; a first memory that stores illumination level data at the start of the fade at an address corresponding to each channel; a second memory that stores illumination level data after the fade ends at an address corresponding to each channel; A third channel stores one or more types of fade progress data that defines the state of change in the illumination level of the channel at an address corresponding to each channel.
memory, and illumination level data at the start of the fade, illumination level data after the end of the fade, and 1 for each channel stored in the first, second, and third memories.
a calculation means for performing fade calculations using fade progress data for each channel of one or more types, and outputting dimming output level data for each channel as a result of the calculation; address data generation means for outputting data to output illumination level data at the start of fade, illumination level data after the end of fade, and fade progress data for each channel to the calculation means; and based on the dimming output level data from the calculation means. and a dimming signal output means for outputting a dimming signal for controlling the output level to the dimming unit for each channel, and the control means outputs illumination level data at the start of the fade, illumination level data after the end of the fade, and 1.
Set one or more fade progression fades in the first, second and third memories, one for each channel.
Any one of one or more fade progress data
This is a light control device characterized in that one can be selected. According to the dimmer device of the present invention, when a certain channel of the lighting load is to be faded, the control means stores the illumination level data at the start of the fade and the data at the end of the fade in the first, second and third memories. Illumination level data and one or more types of fade progress data that define a state of change in illumination level during a fade are stored. Further, one or more fade progress data is selected in the third memory for each channel. On the other hand, the address data generating means includes the first,
Address data is commonly outputted to the second and third memories to output illumination level data at the start of the fade, illumination level data after the end of the fade, and fade progress data for each channel to the calculation means, and the calculation means performs the fade calculation. Execute.
Based on the dimming output level data for each channel which is the calculation result from the computing means, the dimming signal output means outputs a dimming signal to the dimming unit for each channel. Therefore, the control means controls the illumination level data before and after the fade and the fade progress data from the first to
The fade progress data is stored in a third memory, and control is performed to select one or more types of fade progress data. Following this control, the output of each data from the first to third memories and the fade operation performed using each output data are performed by a circuit configuration based on address data from the address data generating means. This eliminates the need for the control means to read data from the first to third memories and perform calculation processing using software, and the fade calculation speed is significantly increased. Embodiment FIG. 1 is a block diagram showing the basic configuration of the present invention. The light control device 40 basically includes an operation unit 41 for inputting light control level data, and a first memory 4 in which the current illumination level for each channel is stored.
2, a second memory 43 in which the illumination level after the end of the crossfade for each channel is stored, a third memory 44 in which the fade progress data for each channel is stored, and a 1, second and third memories 42, 4
For example, set each data to 3,44 CPU
(a central processing unit) or the like;
A fade calculation unit 46 performs fade calculation based on data from the memories 42, 43, and 44, and each dimming unit u1, u2,
. including. FIG. 2 is a block diagram showing a specific configuration related to the fade calculation section 46 in FIG. 1.
The address signal from the first control unit 45 is transmitted from the address output terminal AD to the first, second and third memories 42, 43, 44 via switching circuits 50, 51, 52.
is applied to each address input terminal AD. Further, the upper bits of the address of the first control section 45 are given to the decoder 53, and a write control signal from the first control section 45 is given to the decoder 53 from the output terminal WR. The write control signal is decoded together with the write control signal, and the output from the decoder 53 is applied to write control input terminals WE of the first, second and third memories 42, 43 and 44, respectively. Also, the first control unit 4
The dimming data from 5 is transmitted from the data output terminal DD of the first control unit 45 to the first, second and third memories 4.
2, 43, and 44 data input terminals DI, respectively. In FIG. 2, a second control section 48 that controls the fade calculation section 46 is realized by a counter 54. In FIG. This counter 54 includes an oscillator 96
A clock signal from the input terminal CK is applied to the clock input terminal CK. The output terminal Q0 of the highest bit of the counter 54 is
It is connected to one input terminal of AND gate 55.
The output terminals Q1 to Q8 of the counter 54 are address output terminals, and these output terminals Q1 to Q8 are connected to the first and second addresses via switching circuits 50, 51, and 52, respectively.
It is connected to second and third memories 42, 43, and 44. Output terminal Q9 of the highest bit of the counter 54
outputs a switching signal to the switching circuits 50, 51, and 52, is connected to the other input terminal of the AND gate 55, and is also connected to the first control section 45. Output terminal Q9 of counter 54 is logic “0”
When , the common contact p1 of the switching circuit 50 conducts with the individual contact q1, the common contact p2 of the switching circuit 51 conducts with the individual contact q3, and the common contact p3 of the switching circuit 52 conducts with the individual contact q5. As a result, necessary dimming data is written from the first control section 45 to the first, second, and third memories 42, 43, and 44. When the output terminal Q9 of the counter 54 is logic "0", the common contact p1 of the switching circuit 50 is electrically connected to the individual contact q2, and the common contact p2 of the switching circuit 51 is electrically connected to the individual contact q2.
is electrically connected to the individual contact q4, and the common contact p3 of the switching circuit 52 is electrically connected to the individual contact q6. As a result, the current illumination level data is applied from the data output terminal DO of the first memory 42 to the address input terminal A of the fade calculation unit 46, and the data output terminal DO of the second memory 43 is applied to the input of the fade calculation unit 46. Illumination level data after cross-fade is applied to terminal B, and fade progression data is input from data output terminal DO of third memory 44 to fade data input terminal F of fade calculation section 46. This performs fade calculation control. A different fade progress value can be set for each channel, and this value is used in the fade calculation for each channel. Therefore, depending on the data set by the first control section 45, it is possible to perform complex fades that vary from channel to channel. In addition
The AND gate 55 is for prohibiting the dimming signal output section 47 from holding data at the timing of setting data to the first, second, and third memories 42, 43, and 44. The operation of the light control device 40 will be explained below. Based on the operation of the operation unit 41, the first control unit 45 sets the first to third memories 42 to 44 in a write-enabled state via the decoder 53, and each switching circuit 5
0 to 52 are connected to the individual contacts q1, q3, and q5. The first control unit 45 outputs address data AD and data DT, and the first and second memories 42,
43 is the illumination level data Bi at the start of the fade.
and illumination level data Ai after completion of the fade are written for each channel i. Furthermore, one or more types of fade progress data F are written in the third memory 44 for each channel. Fade progression data is data that defines how the illumination level changes over time over a certain fade period. After this, each switching circuit 50 to 52 has an individual contact q.
2, q4, and q6, and the count value of the counter 54 constituting the second control section 48 based on the clock signal from the oscillator 96 is output as address data. The illumination level data Bi, Ai, and F from the first to third memories 42 to 44 are input to a fade calculation section 46, and a fade calculation represented by the first equation is performed for each channel. The calculation results are individually outputted to the dimming units u1 to un shown in FIG. 1 via the dimming signal output section 47. In this way, in the light control device 40 of this embodiment,
In performing the fade, the first control unit 45 uses the above-mentioned illumination level data Bi, Ai as the first and second
One or more types of fade progress data F are stored in the third memory 44. Thereafter, after performing control to select any one of the fade progression data for each channel, a fade calculation is performed by a circuit configured by the second control section 48 and the fade calculation section 46. That is, the need for the first control unit 45 to perform fade calculation by software processing is eliminated, and the fade calculation process is significantly sped up. In addition, by appropriately determining the fade progress data that the first control unit 45 sets in the third memory 44, it is possible to easily perform complex control in which the illumination level changes differently as the fade progresses for each channel. . FIG. 3 is a block diagram showing the configuration of a second embodiment of the third memory 44. A channel selection signal is applied to the address input terminal AD of the memory 60, and data that distinguishes the type of fade, for example, data "011" for the third fade out of eight types, is sent from the data input DI1 to the channel selection signal. 1 control unit 45 shall set,
The output from the output terminal of the memory 60 is the memory 6
Input terminal of memory 61 as address input of 0
Given to AD. The memory 61 stores, for example, fade progress values of eight fades as a data input D1.
2 is set by the first control unit 45. The output DO of the memory 61 is then used as the fade progress value F of that channel. In this case, the types of fade are limited to a few, and the fade is executed with every channel as belonging to one of them. As shown in the example shown in FIG. 2, there are currently hundreds of channels, each of which is complicated, and setting operations are time-consuming and impractical. Practically speaking, even if several channels are collectively changed by the same fade and there are fades that proceed in parallel at the same time, it is sufficient to have at most 8 to 16 fades. In the case of the embodiment shown in the second figure, when the first control unit 45 sets the fade progress value, it is necessary to write data for at least the number of channels for the types of fades. In the embodiment, it is sufficient to write data only for the type of fade. FIG. 4 is a block diagram showing the configuration of an embodiment of the third memory 44. This embodiment is similar to the previous embodiment, and corresponding parts are provided with the same reference numerals.
In this embodiment, instead of the memory 61, analog faders f1 to fn and an analog multiplexer 62 are used.
This is what was used. In this embodiment, even if the first control unit 45 does not provide the fade progress value of each fade, the faders f1 to fn send the fade progress value to the multiplexer 62.
The analog value given to is used as the fade progression value. The fade progression value selected by multiplexer 62 is converted into a digital value by A/D converter 63 and output. FIG. 5 is a block diagram showing the configuration of a fourth embodiment of the third memory 44. This embodiment is similar to the previous embodiment, and corresponding parts are given the same reference numerals. In this embodiment, one fader f and a memory 64 for storing fade progress characteristic data are used instead of the memory 61.
The output D0 is 3 bits, and 8 types of fades can be selected. This data is applied to address input terminals AD8 to AD10 of memory 64. On the other hand, address lower bit input terminal AD0
- AD7 are given converted data in which the analog value from the fader f is converted into an 8-bit digital value by the A/D converter 63. For example, if the same data as the address is set in the third memory 44 address "00000000" to "11111111",
For the fade "000", the output data of the A/D converter 63 is output as is from the output terminal D0. Also address "100000000" ~ "111111111"
For example, if the data shown in FIG. 6 is set, the output data of the A/D converter 63 is converted as shown in the curve in the figure for fade "001" and is output from the output terminal D0. be done. In this way, eight types of arbitrary fade progression characteristics can be set in the memory 64 through the input signal DI2 from the first control section 45, and which of these data is used can be determined for each channel by the setting data in the memory 60. can be selected. FIG. 7 is a block diagram showing the configuration of a fifth embodiment of the third memory 44. This embodiment is similar to the previous embodiment and corresponding parts are provided with the same reference numerals. Reference numeral 70 is the output of the 3-bit memory 60.
This is a decoder that converts D0 to 8 bits. Reference numbers C1 to C8 are counters, which start counting the clock input φ when the input terminal DI is given "00000000" and the control terminal WE is activated.
When I counted up to "11111111", I realized that
It is detected by NAND gates 90-92, and a low level signal is derived to one input terminal of these AND gates 93-95. As a result, the counting operations of the counters C1 to C8 are stopped. Reference mark B
1 to B8 are buffers, and eight counters C1 to B8 are buffers.
The selected output from C8 is sent to the output line l.
This is for outputting to 1. For example, if the counter C1 is first set to "0", the fade "000" starts from that point. After that, when the counter C2 is also set to "0", the fade "001" also starts from that point. In this example, the same clock is input to each counter C1 to C8, but the clock is applied to each counter C1 to C8 through a rate multiplier, and the division ratio of the rate multiplier is determined in advance. By setting this, you can run multiple time fades with different fade times at the same time. Effects As described above, according to the present invention, when a fade is to be performed in a certain channel of a lighting load, the control means stores the illumination level data at the start of the fade and the data at the end of the fade in the first, second, and third memories. Subsequent illumination level data and one or more types of fade progress data defining a state of change in illumination level during a fade are stored. Further, one or more fade progress data is selected in the third memory for each channel. On the other hand, the address data generating means outputs address data in common to the first, second, and third memories, and generates illumination level data at the start of the fade, illumination level data after the end of the fade, and fade progress data for each channel. The output signal is output to the calculation means, and the fade calculation is executed in the calculation means. Based on the dimming output level data for each channel which is the calculation result from the computing means, the dimming signal output means outputs a dimming signal to the dimming unit for each channel. Therefore, the control means controls the illumination level data before and after the fade and the fade progress data from the first to
The fade progress data is stored in a third memory, and control is performed to select one or more types of fade progress data. Following this control, the output of each data from the first to third memories and the fade operation performed using each output are performed by a circuit configuration based on address data from the address data generating means. This eliminates the need for the control means to read data from the first to third memories and perform calculation processing using software, and the fade calculation speed is significantly increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block diagram showing a specific configuration related to the calculation section in FIG. 1, and FIG. 3 is a block diagram showing a second embodiment of the third memory 44. FIG. 4 is a block diagram showing the structure of a third embodiment of the third memory 44, FIG. 5 is a block diagram showing the structure of the fourth embodiment of the third memory 44, and FIG. A graph showing the relationship between the data stored at the address of the third memory 44 and the output data from the A/D converter 63; FIG. 7 is a block diagram showing the configuration of the fifth embodiment of the third memory 44; FIG. 8 is a block diagram showing the configuration of a typical prior art, and FIG. 9 is a light control device 2 shown in FIG.
1 is a flowchart illustrating the basic operation of step 1. 40... Dimmer device, 42... First memory, 43... Second memory, 44... Third memory, 45... First control section, 46... Fade calculation section, 47... Dimming signal output section, 48... Second control Part, 50, 51, 52...Switching circuit, 53, 70...Decoder, 54, C1 to C8
...Counter, 60, 61, 64...Memory, 62...
Multiplexer, 63...analog/digital converter.

Claims (1)

[Scope of Claims] 1. Control means for outputting lighting level data at the start of a fade for each channel of a lighting load, lighting level data after the end of the fade, and fade progress data for each channel; and lighting at the start of a fade. A first memory stores level data at an address corresponding to each channel, a second memory stores illumination level data after fading at an address corresponding to each channel, and defines the state of change in illumination level for each channel. A third section that stores one or more types of fade progress data in an address corresponding to each channel.
memory, and illumination level data at the start of the fade, illumination level data after the end of the fade, and 1 for each channel stored in the first, second, and third memories.
a calculation means for performing fade calculations using fade progress data for each channel of one or more types, and outputting dimming output level data for each channel as a result of the calculation; address data generation means for outputting data to output illumination level data at the start of fade, illumination level data after the end of fade, and fade progress data for each channel to the calculation means; and based on the dimming output level data from the calculation means. a dimming signal output means for outputting a dimming signal for controlling the output level of the dimming unit for each channel; A light control device characterized in that a plurality of fade progress data are set in first, second and third memories, and one or more of the fade progress data is selected for each channel. .