JPH0340917B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to a light control device for use on a stage or in a studio. BACKGROUND TECHNOLOGY A light control device is a device that realizes the illumination levels of multiple lighting loads set by an operation unit and realizes mutual transition of scenes (scenes) that are a collection of illumination levels of multiple lighting loads. , it is necessary to realize operations on the operating unit faithfully, smoothly, and without time delay. In recent years, the number of controlled lighting loads or dimmer units (devices that control the lighting level of the lighting load by controlling the phase of the power supply voltage to the lighting load based on the dimming signal from the dimmer) has increased. The problem has been how to process dimming calculations quickly and realize a device with good response. If a cross fade (time fade) is to be performed automatically over time, the light control device 1 shown in FIG. 5 can be considered. The configuration of the light control device 1 will be explained with reference to FIG. 5. In a scene where a fade is performed, a memory 2 that stores illumination level data Bi at which the fade is started, and a memory 3 that stores illumination level data Ai at the end of the fade are provided. Further, a memory 4 is provided in which fade progress data F that defines the fade progress state of these circuits is stored. An arithmetic circuit 5 is provided which reads data from the memories 2 to 4 and performs the arithmetic operation basically shown as Bi+F(Ai-Bi)...(1), and its output O is used to control the illumination by a dimming unit (not shown). It is applied to an output section 6 that outputs level data. A control unit (CPU) 7 and a decoder 8 for setting the contents of the memories 2 to 4, as well as a counter 9 and an oscillator 10 are provided. The address signal output terminal AD of the control section 7 is applied to each address input terminal AD of the memories 3 and 2 via switching circuits 11 and 12 that collectively switch the address lines. The upper bits of those addresses are input to the decoder 8, where they are decoded together with the control signal ST from the CPU 17, and the outputs are the write control input terminal WE of memory 3, the write control input terminal WE of memory 2, and the write control input terminal WE of memory 4. It is applied to a write control input terminal WE, a count value write control input terminal WE and a read control input terminal OE of the counter 9, respectively.
Oscillator 10 provides a counting clock to counter 9. The data input/output terminal DT of the CPU 7 is connected to the data input terminal DI of the memories 2 to 4 and the data input/output terminal DT of the counter 9. In this configuration, when performing the above-mentioned time fade, first the switching circuits 11 and 12 are connected to the contacts a11 and
c11: Switch so that a12 and c12 are connected respectively, and store the A scene level Ai and B scene level of each channel in memories 3 and 2.
Write Bi to memory 4 and counter 9,
Write the initial value (for example, zero) of the fade progress value F. Thereafter, if the switching circuits 11 and 12 are switched so that the contacts b11, c11; b12, c12 are connected, respectively, the fade calculation is performed by the calculation control section 13 defined by the counter. That is, before a certain fade is started, the CPU 7 writes the level data Bi and Ai at the time of starting and ending the fade to the memories 2 and 3, respectively, and also writes the initial value of the fade progress value F to the memory 4.
write to. Thereafter, the calculation of the first equation is performed in the calculation circuit 5 using the level data Bi, Ai from the memories 2 and 3 and the fade progress value F. At this time
In order to input the fade progress value F that continuously changes as the fade progresses to the arithmetic circuit 5, the CPU 7 reads out the fade progress value F from the memory 4 over the entire period of the fade operation, and inputs the fade progress value F to the arithmetic circuit 5.
perform the action of inputting. In such an operation, the time spent reading out the fade progress value F from the memory 4 occupies a large proportion of the operating time of the CPU 7.
The problem arises that the restrictions placed on other operations during the 7 fade period are increased. Such a problem becomes particularly noticeable when a plurality of types of fade progress are set for each of a plurality of lighting loads and progress simultaneously. Further, in the light control device, various input operations such as input of illumination level data are often performed even while fading is in progress, and in such a case, the CPU 7 has to process many operations. Therefore, when the plurality of types of fades are progressing simultaneously, it becomes difficult for the CPU 7 to read out the fade progress values from the memory 4 at a sufficiently high speed, and the change in the illumination level realized in the fade operation becomes difficult. This poses a problem in that it undesirably changes in a step-like manner. Purpose The purpose of the present invention is to solve the above-mentioned technical problems,
A light control device that speeds up the calculation process by using a circuit configuration to calculate the illumination level data necessary for performing a fade operation, and improves usability by eliminating the need for software processing related to the above calculation process. The goal is to provide the following. Structure of the Invention The structure of the present invention to achieve the above object includes a control means for outputting illumination level data of a plurality of scenes of a plurality of dimming units, and a control means based on speed data that defines the advancing speed of the fade. fade progress data output means for outputting fade progress data; speed data output means for outputting the speed data determining the progress speed of the fade to the fade progress value data output means; and lighting of each dimming unit output from the control means. A memory section that stores level data in addresses corresponding to each dimming unit, illumination level data at the start and end of fade of each dimming unit read from the memory section, and output from a fade progress value data output means. a calculation unit that performs fade calculation based on the fade progress data obtained and outputs the dimming output level data of each dimming unit as a result of the calculation; and a dimming signal output section that outputs a dimming signal for controlling the illumination level, and the control means stores the speed data and the fade start and fade end information in the speed data output means and the storage section prior to the fade operation. This is a light control device characterized in that it writes illumination level data at a given time, reads the illumination level data, and outputs it to an arithmetic unit. With such a dimming device, the fading operation is performed as a conversion of illumination levels between scenes of a plurality of dimming units. The control means writes illumination level data at the start and end of the fade for each dimming unit into the storage section, and writes speed data into the speed data output means. Furthermore, the written illumination level data is read from the storage section and output to the calculation section. On the other hand, the fade progress data output means outputs fade progress data that defines the progress speed of the fade to the calculation means based on the speed data from the speed data output means. As a result, the fade calculation is performed in the calculation section over the entire fade period by the circuit configuration. As a result, the arithmetic processing is compared with an operation in which the control means continuously reads the fade progress data from the means for storing the fade progress data over the entire fade period and inputs it into the arithmetic means;
Fade calculations can be performed much faster.
Further, such fade calculation does not need to be performed under the control of the control means during the fade period,
Even if multiple fades occur simultaneously,
The speed of fade calculation is reduced, and therefore problems such as changes in illumination level realized as a fade operation becoming step-like can be resolved. Furthermore, the control means is no longer required to perform control to perform fade calculations during the fade period, and can effectively process processes other than fade calculations, thereby significantly improving the usability of the light control device. Embodiment FIG. 1 shows a light control device 21 according to an embodiment of the present invention.
The basic configuration is shown below. The fade progress data F is
Count data generated from the counter 22 is used. The control unit (CPU) sets data to the memories 23 and 24, which are storage units, and the counter 22.
It is 25. Address signal output terminal of CPU25
AD is connected to memory 2 through switching circuits 26 and 27.
3 and 24 address input terminals AD.
The upper bits of those addresses are input to the decoder 28 and decoded at both the output terminal ST from the control signal from the CPU 25, and the output is sent to the write control input terminal WE of the memory 23, the write control input terminal WE of the memory 24, These signals are respectively applied to count value write control input terminals WE of the counter 22.
Oscillator 29 provides a counting clock to counter 22. The data input/output terminal DT of the CPU 25 is connected to the memories 23 and 24 and the data input terminal DI of the counter 22. When performing a time fade in this configuration, first the contact a2 is changed in the switching circuits 26 and 27.
6, c26; A27, c27 are switched to be conductive, and the A scene level Ai and the B scene level of each channel are stored in the memories 23 and 24.
Write Bi and fade progress value F to counter 22.
Write. Thereafter, the contacts a26, c26; a27, c27 in the switching circuits 26, 27 are set to conduct, respectively. Thereafter, fade calculations are repeatedly performed by the calculation control section 30 implemented by a counter or the like. Counter 22 counts the clock input from oscillator 29, and the count value automatically changes by one.
The counted value is output as the fade progress value F to the calculation circuit 31 and is calculated. The calculation result is provided to an output section 32 which outputs a dimming level signal to the dimming unit. The CPU 25 does not need to be involved in any data setting until the end of a fade and the start of the next fade. Therefore, the first
Although not shown in the figure, the CPU 25 can be devoted to input processing from the operation unit and the like. Furthermore, by using a plurality of counters 22, it is possible to easily advance a plurality of time fades simultaneously. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. In the configuration shown in FIG. 1, a counter 22 for counting a fade progress value F is provided with a rate generator 33 which is a speed data output means realized by a frequency dividing circuit of a clock φ1 that controls a fade time, and a delay time. A timer 34 is additionally provided as a fade progress data output means for limiting the fade start delay time. The memory 23 is a memory that stores the illumination level for each channel of scene A. The memory 24 is a memory that stores the illumination level for each channel of scene B. The CPU 25 is a control processor for setting data in the counter 22, rate generator 33, timer 34, and memories 23 and 24. The decoder 28 selects each element according to the address signal of the CPU 25 and provides a write control signal WE to each element. Buffers B1 to B4 are provided. Output control input
When OC is low level, the input data is output (ON) as is, and when the input is high level, the output is open (OFF). Batsuhua
B1 and B2 connect the address lines given to the memories 23 and 24 to the output of the counter 22.
Switch to either the address terminal AD output from the CPU 25 (see Table 1). This is Figure 1

This corresponds to the switching circuits 26 and 27 in [Table]. Buffers B3 and B4 connect the lines of the data input/output terminals DT of the memories 23 and 24 to the data output terminal DT of the CPU 25 at the time of input, and to the fade calculation circuit 31 at the time of output.
This is for switching to connect to input terminals A and B of. These switching operations are performed by the most significant bit Q9 of the output of the arithmetic control section 30. Therefore, Q9 of the arithmetic control unit 30 is "0" and the terminal Q1
~ While Q8 is counting from "00000000" to "11111111", buffer B2 is ON, and buffer B1,
Since B3 and B4 are off, fade calculation control is performed by the calculation control section 30. then output
When Q9 becomes "1", the buffers B1, B3, B4
turns ON, and buffer B2 turns OFF. Therefore, the data line and address line
Connects to the 25th side. At the same time, the interrupt input INT to the CPU 25 becomes active, so
The CPU 25 enters an interrupt process to write data to each element as necessary. For example, when fading to a new scene, the data previously written to the memory 23 is written to the memory 24 as is, and level data for each channel is newly written to the memory 23 for the new scene.
Then, data corresponding to the delay time until the start of the fade (delay time) is written to the timer 34, and the time from the start to the end of the fade (fade time) is written.
Data corresponding to the fade progress value is written to the rate generator 33, and "0" is written to the counter 22 that counts the fade progress value. This completes the interrupt processing. Even if a fade is in progress, unless there is a need to start a new fade, the CPU 25 does nothing even if it enters interrupt processing and returns to normal processing. After the interrupt processing is completed, the output Q9 of the arithmetic control unit 30 returns to “0” again, the outputs Q1 to Q8 count “00000000” to “11111111”, and the fade arithmetic control by the arithmetic control unit 30 is performed as described above. will be carried out. In this way, fade calculation and data setting are repeated periodically. Once each data is set, the time fade automatically advances according to the fade progress value F created by the counter 22, rate generator 33, and timer 34, and each time fade changes as the fade progresses. The output level of the channel is determined by the fade calculation circuit 3 under the control of the calculation control section 30.
1 is periodically calculated and output to the output section 32. Initially, the fade progress value F is 0, and the state of scene B is output by the calculation of the first equation in the fade calculation circuit. Therefore, if you count down every second to 0,
Its output Q changes from 0 to 1. As a result, the clock from the output Q of the rate generator 33 is applied to the counter 22 via the AND gate 35. Therefore, from this point on, the fade actually begins to progress. Since the input clock φ1 of the rate generator 33 is 255Hz, the CPU 2
5 is set as f, the rate generator 33 outputs a frequency of 255/f [Hz]. Therefore, it takes f seconds for the counter 22 to count from "00000000" to "11111111" as follows: 255/(255/f)=f (3). FIG. 3 is a block diagram showing the configuration of the rate generator 33. The rate generator 33 is
The write control signal WE is input, and the CPU2
5, a counter 37 to which the clock input φ1 is input, and a comparator 38 to which the outputs of the latch circuit 36 and the counter 37 are respectively input. Comparator 38 derives a high level signal when the respective inputs from latch circuit 36 and counter 37 are equal. FIG. 4 is a block diagram showing the structure of the timer 34. The timer 34 includes a down counter 39, an initial state detection circuit 40 for detecting the initial state indicated by "00000000", and a logic gate 41 to which the output from the initial state detection circuit 40 is fed back. In this way, in f seconds, the output Q of the counter 22, that is, the input F of the arithmetic circuit 31 changes from "00000000" to "11111111" at a constant speed. As a result, the output O of the output section 32
will fade from the B-scene state to the A-scene state. When the output of the counter 22 reaches "11111111", the NAND circuit G prohibits clock input, and counting stops there. As described above, in the light control device 21 of the present embodiment, the CPU 25 controls the fade calculation by writing the level data Bi, Ai at the start of the fade and at the end of the fade into the memories 24, 23, Write the numerical value f that specifies the progress speed of the fade into the latch circuit 36 of 33, and also write the level data Bi, Bi, from the memories 24 and 23.
This is the operation of outputting Ai to the arithmetic circuit 31. As for the fade calculation during the fade period, as described above, the calculation circuit 31 uses the count value from the counter 22 as the fade progress value data F and performs the fade calculation expressed by the first equation. Therefore, the fade calculation process is greatly speeded up. In addition, the CPU 25 does not need to control the execution of calculation processing during the fade calculation period, and as a result, even when multiple fades are progressing in parallel, the CPU 25 controls the fade calculation. It is possible to prevent problems such as the fade calculation process taking more time than in the case where the change in illumination level that appears as a fade operation becomes step-like. In addition, during the fade operation, the CPU 25 does not need to control the fade calculation, and as a result, various other input processes can be executed efficiently, and the usability of the dimming device 21 is greatly improved. Improved. Effects As described above, according to the present invention, the control means writes the illumination level data at the start and end of the fade for each dimming unit into the storage section, and writes the speed data into the speed data output means. Furthermore, the written illumination level data is read from the storage section and output to the calculation section. On the other hand, the fade progress data output means outputs fade progress data that defines the progress speed of the fade to the calculation means based on the speed data from the speed data output means. As a result, the fade calculation is performed in the calculation section over the entire fade period by the circuit configuration. As a result, the arithmetic processing is compared with an operation in which the control means continuously reads the fade progress data from the means for storing the fade progress data over the entire fade period and inputs it into the arithmetic means;
Fade calculations can be performed much faster. Furthermore, such a fade operation does not need to be performed under the control of a control means during the fade period, and even if multiple fades occur simultaneously, the speed of the fade operation will decrease, and therefore the fade operation will not be performed as a fade operation. It is possible to eliminate problems such as changes in the realized illumination level becoming step-like. In addition, the control means eliminates the need to perform control to perform fade calculations during the fade period,
Processes other than fade calculation can be effectively processed, and the usability of the light control device is greatly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block diagram showing the configuration of a light control device 21 according to an embodiment of the present invention, and FIG. 3 is a rate generator 33 in the light control device 21. FIG. 4 is a block diagram showing the structure of the timer 34, and FIG. 5 is a block diagram showing the structure of the conventional light control device 1. 21...Dimmer, 22...Counter, 23, 24
...Memory, 25...CPU, 26, 27...Switching circuit,
29... Oscillator, 30... Arithmetic control unit, 31... Arithmetic circuit, 33... Rate generator, 34... Timer.

Claims (1)

[Scope of Claims] 1. A control means for outputting illumination level data of a plurality of scenes of a plurality of dimming units, and a fade progress data output means for outputting fade progress data based on speed data that defines the progress speed of the fade. and speed data output means for outputting the speed data that determines the progress speed of the fade to the fade progress value data output means; and illumination level data of each dimming unit outputted from the control means to an address corresponding to each dimming unit. A fade operation is performed using the lighting level data read from the memory unit at the start and end of the fade of each dimming unit and the fade progress data output from the fade progress value data output means. a calculation section that outputs the dimming output level data of each dimming unit as a result of the calculation, and a dimming signal that controls the illumination level of each dimming unit based on the dimming output level data from the computing section. the control means writes speed data and illumination level data at the start of the fade and at the end of the fade into the speed data output means and the storage section prior to the fade operation; A light control device characterized in that level data is read out and output to a calculation section.