JPH0343597B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an electronic device equipped with an alarm operation and a timer operation, such as a television receiver with a clock, which uses an alarm signal, which is an audible pulse signal from a clock circuit, to perform settings. The purpose of the present invention is to provide a switching device that allows easy selection of continuous operation of a television receiver and alarm operation using an alarm sound from the time when the television receiver is switched on.

An embodiment of the present invention will be described below by taking a television receiver with a clock as an example. In the figure, 1 is the power supply, 2 is the power switch, and 3 is the NAND
The RS flip-flop circuit consists of gates 4 and 5, and the set terminal S is connected to the power supply 1 through a resistor 6.
It is also connected to an input terminal 7 to which an alarm signal from a clock circuit (not shown) is applied. Reference numeral 8 denotes an initial setting transistor, which has resistors 9, 10 and a capacitor 11 forming a differentiating circuit at its base, and becomes conductive momentarily by a positive pulse obtained by the action of the differentiating circuit when the power switch 2 is closed. 12 is a NAND gate, one input terminal a of which is connected to the power supply via a resistor 13, and a discharge diode 14 and a capacitor 15 connected in series between the set terminal S of the RS flip-flop circuit 3 and the ground. connected to the connection point. 16, 17, 18, 1
9, 20, 21, 22 are elements constituting a stabilized power supply circuit, 16 is a series control transistor, 17,
18 is a transistor for error amplification, 19 and 20 are output voltage dividing resistors, 21 is a Zener diode for providing a reference voltage, and 22 is a series stabilizing resistor thereof.

A switching transistor 23 is inserted in series between the base of the series control transistor 16 and the emitter of the error amplification transistor 18, and the base is connected to the output terminal Q of the RS flip-flop circuit 3 via a current limiting resistor 24. is connected to. 25 is a switching transistor for starting, whose base is connected to the output terminal Q of the RS flip-flop circuit 3 via a current limiting resistor 26, whose collector is connected to the power supply, and whose emitter is connected to a capacitor 27 and a backflow prevention diode 28. It is connected to the base of the error amplification transistor 17 through the transistor 17. Here, 29 and 30 are resistors for discharging the capacitor 27. Reference numeral 31 denotes a second series control transistor, the base of which is connected to a Zener diode 32 for reference voltage. 33 is a load connected to the output end of the stabilized power supply circuit, which corresponds to the audio amplifier circuit and the television circuit excluding the speaker. 34 is a load connected to the output terminal of the series control transistor 31, which corresponds to an audio amplification circuit, and the audio signal from the load 33 is connected to the input terminal of the variable resistor 3 for volume adjustment.
5, applied via resistor 36. 37 is a speaker.

Further, 38 is a switching transistor whose emitter is connected to the power supply via a resistor 39, and whose collector is connected to the base of the series control transistor 31.
The base is connected to the other output terminal Q of the RS flip-flop circuit 3 via a current limiting resistor 40. 41 and 42 are backflow prevention diodes connected in series in opposite directions, and are connected to the input terminal 7 and the load 3.
4 input terminal. 43 is an inverter whose input side is connected to the collector of the series control transistor 31 via a resistor 44, and whose output terminal is connected to the other input terminal b of the NAND gate 12, and which is connected to the diode 41 via a resistor 45.
and 42 connection points. 46 is the base of the switching transistor 23 and the inverter 43
A backflow prevention diode 47 is inserted between the input terminal of the inverter 43 and a reset switch 47 is inserted between the input terminal of the inverter 43 and the ground.

Next, its operation will be explained.

Assume that the reset switch 47 is now open.
When the power switch 2 is closed, the transistor 8 becomes conductive for a moment due to the action of the differential circuit, and its collector potential becomes low level. That is, R.S.
The flip-flop circuit 3 is set when the set terminal becomes low level, its Q output becomes high level, and its output becomes low level. On the other hand, at this time, the capacitor 15 completes charging with the passage of time, and the transistor 8 becomes irrelevant to the subsequent operation.

When the Q output of the RS flip-flop circuit 3 becomes high level, the respective switching transistors 23 and 23 are connected via the resistors 24 and 26, respectively.
25 is conductive. When the transistor 25 is turned on, its output is applied to the base of the error amplification transistor 17 via the capacitor 27 and the diode 28, making the transistor 17 conductive. On the other hand, since the switching transistor 23 is conductive as described above, the error amplification transistor 18 and the series control transistor 1
6 is conductive. In this way, the output voltage of the stabilized power supply circuit rises and enters steady operation, causing the load 33 to operate.

At this time, the Q of the RS flip-flop circuit 3 is
Since the output is at a low level, the switching transistor 38 also becomes conductive, and the power supply voltage is applied to the reference voltage diode 32 via the series stabilizing resistor 39, making the series control transistor 31 conductive, and the output voltage causes the load 34 to become conductive. make it work.
As a result, the audio signal from the load 33 is input to the load 34 via the volume adjusting variable resistor 35 and the resistor 36, and amplified audio is obtained from the speaker 37. In other words, the television receiver becomes operational.

At this time, one input terminal a of the NAND gate 12 is at a high level because the capacitor 15 is charged, and the other input terminal b is at a high level.
Since the input of the inverter 43 is at a high level and its output is at a low level, the output of the NAND gate 12 becomes a high level and does not reset the RS flip-flop circuit 3. Further, since the diode 42 is also in a reverse bias state, it does not affect the circuit operation.

Here, if the reset switch 47 is momentarily closed (therefore, it opens immediately after closing),
The input of the inverter 43 becomes low level,
The other input terminal b of the NAND gate 12 becomes high level. At this time, the other input terminal a of the NAND gate 12 is also at a high level due to completion of charging of the capacitor 15, so the output of the NAND gate 12 becomes a low level, the RS flip-flop circuit 3 is reset, and its output is inverted. do. That is, since the Q output becomes low level and the output becomes high level, switching transistors 23, 25, and 38 are all cut off, and loads 33 and 34 stop operating.

This state is a so-called standby state, and this state continues until the alarm signal 48 from the clock circuit is input to the input terminal 7.

In this state, when the alarm signal 48 is applied to the input terminal 7, the RS flip-flop circuit 3 is set at its first falling edge, and the above-described operation is performed. That is, when the set time comes, the television receiver starts operating. In this case, the alarm signal 48 is only input for a set time, for example, one minute, but due to the function of the RS flip-flop circuit 3,
Television receivers operate continuously.

Next, if the reset switch 47 is kept closed, the standby state is entered as described above. In this state, when the alarm signal 48 is applied to the input terminal 7, the diode 14 is turned off during the low level period. becomes conductive and the charge in the capacitor 15 is discharged through the diode 14, so that eventually
Since one input terminal a of the NAND gate 12 is at a low level and the other input terminal b is at a high level, the output of the NAND gate 12 is at a high level and the RS flip-flop circuit 3 is not reset. At this time, the high level output of the inverter 43 is passed through the resistor 45 to the diode 4.
1 and 42, the diode 41 becomes conductive when the alarm signal 48 is at a low level, and the intersection potential between the diodes 41 and 42 becomes a low level.
This change in intersection potential is applied to the load 34 via the diode 42.

On the other hand, at this time, the Q output of the RS flip-flop circuit 3 becomes high level, but since the other end of the resistor 24 is connected to the ground via the diode 46 and reset switch 47, the base of the switching transistor 23 becomes low level. level,
The switching transistor 23 is in a cut-off state, the stabilized power supply circuit does not operate, and the load 33 also does not operate. On the other hand, since the output of the RS flip-flop circuit 3 is at a low level, the switching transistor 38 becomes conductive, the load 34 becomes operational, and the signal input through the diode 42 is amplified instead of the audio signal from the load 33. Then, an alarm sound is generated from the speaker 37.

In this state, the time that the alarm signal 48 is applied is usually finite, so when the alarm signal 48 disappears, the capacitor 15 is connected to the resistor 1.
3, and after a charging time constant determined by this resistor 13 and capacitor 15 has elapsed,
One input terminal a of the NAND gate 12 becomes a high level, and since the reset switch 47 is closed, the other input terminal b also becomes a high level, and the output of the NAND gate 12 becomes a low level. As a result, the RS flip-flop circuit 3 is reset, its output is inverted, and the load 34 also stops operating, returning to a so-called standby state.

According to this configuration, when the reset switch 46 is open, the loads 33 and 34 are activated by the alarm signal 48 that is generated at the set time.
When the reset switch 46 is closed, only the load 34 can be operated by the alarm signal 48, and an alarm sound can be generated in place of the audio signal from the load 33. can. At this time, when the alarm signal 48 is no longer applied, the load 3
4 will also automatically stop operating. Furthermore, the current during standby can be kept to a very small level. At this time, if CMOS is used for the NAND gates 4, 5, 17 and the inverter 43, the standby current becomes even smaller.

In the above embodiments, a television receiver with a clock has been described as an example, but the present invention is not limited to this.

As explained above, according to the present invention, timer operation and alarm operation of multiple loads can be realized by inputting a finite length pulse signal in the audible range.
Its practical effects are extremely large.

[Brief explanation of drawings]

The drawing is a circuit diagram of a switching device in one embodiment of the present invention. 1...Power supply, 2...Power switch, 3...RS
Flip-flop circuit, 4, 5, 12...
NAND gate, 7...Alarm signal input terminal,
15... Capacitor, 16, 31... Series control transistor, 17, 18... Error amplification transistor, 21, 32... Zener diode, 3
3, 34...Load, 37...Speaker, 28,4
1, 42, 46... Diode for backflow prevention, 47
...Reset switch.

Claims (1)

[Claims] 1 By inputting an audible pulse signal,
A first load consisting of an audio amplification circuit, a speaker, etc., and a second load constituting a television circuit other than the first load are simultaneously operated, and the first load is operated even after the audible pulse signal has been inputted. and the means of
a second means for operating only the first load when an audible pulse signal is input; and a second means for operating only the first load while the audible pulse signal is applied;
a third means for stopping the operation of the second means activated by the audible pulse signal after a certain period of time has elapsed when the audible pulse signal is no longer input; and a fourth means for canceling the operation of the first means. A switching device comprising: means.