JPH0344032A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0344032A
JPH0344032A JP17962789A JP17962789A JPH0344032A JP H0344032 A JPH0344032 A JP H0344032A JP 17962789 A JP17962789 A JP 17962789A JP 17962789 A JP17962789 A JP 17962789A JP H0344032 A JPH0344032 A JP H0344032A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
film
silicon film
forming
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17962789A
Other languages
Japanese (ja)
Inventor
Akira Mitsui
光井 章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP17962789A priority Critical patent/JPH0344032A/en
Publication of JPH0344032A publication Critical patent/JPH0344032A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To process the side surface of a polycrystalline silicon electrode in the form of a normal taper, by forming a first polycrystalline silicon film on a semiconductor substrate via an insulating film, selectively etching at the same time a doped polycrystalline silicon film which is formed continuously, and forming a pattern. CONSTITUTION:A thermal oxidation film 2 is formed on a semiconductor substrate 1. A polycrystalline silicon film 3a is formed by low pressure CVD method, and a polycrystalline silicon film 3b is formed while PH3 gas is continuously introduced. The polycrystalline silicon films 3a, 3b of two-layer structure formed in the preceding process are selectively etched by dry etching method, thereby forming a pattern. Isotropic etching is performed under the condition that difference in etching rate is generated by phosphorus concentration in the polycrystalline silicon film, and thus the side face shape is turned into a normal taper. Thereby excellent step coverage of an interlayer insulating film and a conducting film formed in the subsequent process can be realized.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、多結晶シリコン層を電極とする半導体装置の
製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a polycrystalline silicon layer as an electrode.

従来の技術 以下に従来の多結晶シリコンを電極として有する半導体
装置について説明する。第2図(a)〜(C)は、従来
の半導体装置の製造工程図の一例を示すものである。第
2図において1は半導体基板、2は酸化膜、3は多結晶
シリコン膜、4は酸化膜、5は導電膜である。以上のよ
うに構成された半導体装置について、以下、その製造工
程を説明する。まず、第2図(a)のように、半導体基
板1上に熱酸化膜2を形成する。そして、この多結晶シ
リコン膜2を形成した後、第2図(b)のように、リン
等の不純物をドーピングして、多結晶シリコン膜2の抵
抗値を低下させる。次に、第2図(C)のように、多結
晶シリコン膜2を選択的にエツチングし、所望のパター
ンを形成する工程を経た後に、酸化膜4をCVD法によ
り形成し、ついで導電膜5を形成する。導電膜5はパタ
ーン形成され、配線として使用される。
2. Description of the Related Art A conventional semiconductor device having polycrystalline silicon as an electrode will be described below. FIGS. 2(a) to 2(C) show an example of a manufacturing process diagram of a conventional semiconductor device. In FIG. 2, 1 is a semiconductor substrate, 2 is an oxide film, 3 is a polycrystalline silicon film, 4 is an oxide film, and 5 is a conductive film. The manufacturing process of the semiconductor device configured as described above will be described below. First, as shown in FIG. 2(a), a thermal oxide film 2 is formed on a semiconductor substrate 1. After forming this polycrystalline silicon film 2, impurities such as phosphorus are doped to lower the resistance value of the polycrystalline silicon film 2, as shown in FIG. 2(b). Next, as shown in FIG. 2(C), after a step of selectively etching the polycrystalline silicon film 2 to form a desired pattern, an oxide film 4 is formed by the CVD method, and then a conductive film 5 is formed. form. The conductive film 5 is patterned and used as wiring.

発明が解決しようとする課題 しかしながら、上記の従来の製造工程では、多結晶シリ
コン膜を選択的にエツチングし、パターンを形成する工
程で、多結晶シリコン電極の側面が切立つ形状となるた
め、後工程で形成される酸化膜4および導電膜5の段差
被覆性が劣化する。
Problems to be Solved by the Invention However, in the above-mentioned conventional manufacturing process, the polycrystalline silicon film is selectively etched to form a pattern, and the sides of the polycrystalline silicon electrode become steeply shaped. The step coverage of the oxide film 4 and the conductive film 5 formed in the process deteriorates.

そのため、配線加工された導電膜5の同層リークや信頼
性不良等の問題が発生する。
Therefore, problems such as leakage in the same layer of the conductive film 5 processed with wiring and poor reliability occur.

本発明は上記従来の問題点を解決するもので、パターニ
ングされた多結晶シリコン電極の側面形状を改善し、後
工程で形成される層間絶縁膜、導電膜の良好な段差被覆
性を提供することを目的とする。
The present invention solves the above-mentioned conventional problems, and aims to improve the side surface shape of a patterned polycrystalline silicon electrode and provide good step coverage for interlayer insulating films and conductive films formed in subsequent steps. With the goal.

課題を解決するための手段 この目的を多達成するために本発明の半導体装置の製造
方法は半導体基板上に絶縁膜を介して第1の多結晶シリ
コン膜を形成し、さらに連続してドーピングガスを導入
しながら第2の多結晶シリコン膜を形成する工程を経た
後、前記第1.第2の多結晶シリコン層を選択的にエツ
チングしパターンを形成する工程を有している。
Means for Solving the Problems In order to achieve many of the objects, the method for manufacturing a semiconductor device of the present invention includes forming a first polycrystalline silicon film on a semiconductor substrate via an insulating film, and then continuously applying a doping gas. After passing through the step of forming a second polycrystalline silicon film while introducing the first. The method includes a step of selectively etching the second polycrystalline silicon layer to form a pattern.

作用 この発明によると、多結晶シリコン層を選択的にエツチ
ングする際、ドーピングされている第2の多結晶シリコ
ン膜の方がドーピングされていない第1の多結晶シリコ
ン膜よりもエツチング速度が速くなる条件を選ぶことに
より、多結晶シリコン電極寸法は、下部よりも上部にお
いて小さくなる。したがって多結晶シリコン電極の側面
形状は順テーパとなり、後工程で形成される層間絶縁膜
、導電膜の良好な段差被覆性を達成することができる。
According to the present invention, when selectively etching a polycrystalline silicon layer, the etching rate of the doped second polycrystalline silicon film is faster than that of the undoped first polycrystalline silicon film. By choosing the conditions, the polycrystalline silicon electrode dimensions are smaller at the top than at the bottom. Therefore, the side surface shape of the polycrystalline silicon electrode becomes a forward taper, and it is possible to achieve good step coverage of an interlayer insulating film and a conductive film formed in a later process.

実施例 以下、本発明の一実施例について、図面を参照しながら
説明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図(a) 、 (b)は本発明の実施例における半
導体装置の製造方法を示す工程図である。第1図におい
て1は半導体基板、2は酸化膜、3aはドーピングされ
ていない多結晶シリコン膜、3bはリンがドーピングさ
れている多結晶シリコン膜、4は酸化膜、5は導電膜で
ある。
FIGS. 1(a) and 1(b) are process diagrams showing a method for manufacturing a semiconductor device in an embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate, 2 is an oxide film, 3a is an undoped polycrystalline silicon film, 3b is a phosphorus-doped polycrystalline silicon film, 4 is an oxide film, and 5 is a conductive film.

以上のように構成された半導体装置において以下その製
造工程を説明する。
The manufacturing process of the semiconductor device configured as described above will be explained below.

第1図(a)のように、まず、半導体基板1上に熱酸化
膜2を形成する。次に減圧CVD法により多結晶シリコ
ン膜3aを形成し連続してPH3ガスを導入しながら多
結晶シリコン膜4を形成する。
As shown in FIG. 1(a), first, a thermal oxide film 2 is formed on a semiconductor substrate 1. As shown in FIG. Next, a polycrystalline silicon film 3a is formed by low pressure CVD, and a polycrystalline silicon film 4 is formed while continuously introducing PH3 gas.

PH3ガスを導入することにより、膜の成長速度は低下
するが炉内温度分布、圧力を調整することにより、切−
な膜厚分布を得ることができる。
By introducing PH3 gas, the growth rate of the film decreases, but by adjusting the temperature distribution and pressure inside the furnace, the cutting speed can be reduced.
It is possible to obtain a film thickness distribution.

次に、第1図(b)のように、前工程で形成した2層構
造の多結晶シリコン膜3a、3bをドライエツチング法
により選択的にエツチングし、パターン形成を行う。エ
ツチング条件は、異方性エツチングでパターニングを完
了した後、等方性エツチングを施す方法もしくは異方性
と等方性の中間の条件で最初からエツチングする方法の
2通りが挙げられる。とちらの方法においても等方性エ
ツチングの条件は多結晶シリコン膜中のリン濃度により
エツチング速度に差が出る条件を採用することで、多結
晶シリコン電極の側面形状は順テーパ(すなわち、電極
の断面形状として台形)となり、後工程で形成される層
間絶縁膜、導電膜の良好な段差被覆性を達成することが
できる。
Next, as shown in FIG. 1(b), the two-layered polycrystalline silicon films 3a and 3b formed in the previous step are selectively etched by dry etching to form a pattern. There are two types of etching conditions: a method in which patterning is completed by anisotropic etching and then isotropic etching is performed, or a method in which etching is performed from the beginning under conditions intermediate between anisotropic and isotropic. In both methods, the isotropic etching conditions are such that the etching rate varies depending on the phosphorus concentration in the polycrystalline silicon film, so that the side shape of the polycrystalline silicon electrode is forward tapered (i.e., the side surface of the electrode is tapered). The cross-sectional shape is trapezoidal), and it is possible to achieve good step coverage of an interlayer insulating film and a conductive film formed in a later process.

発明の効果 以上のように本発明によれば、半導体基板上に絶縁膜を
介して第1の多結晶シリコン膜を形成し、さらに連続し
て形成されるドーピングされた多結晶シリコン膜を同時
に選択的にエツチングしパターン形成することにより、
多結晶シリコン電極の側面形状を順テーパに加工するこ
とで、品質の優れた半導体装置を実現できる。
Effects of the Invention As described above, according to the present invention, a first polycrystalline silicon film is formed on a semiconductor substrate via an insulating film, and a doped polycrystalline silicon film that is continuously formed is simultaneously selected. By selectively etching and forming patterns,
By processing the side surface shape of the polycrystalline silicon electrode into a forward tapered shape, a semiconductor device with excellent quality can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al、 (b)は本発明の製造方法を示す工程
図、第2図(a)〜(C)は従来法による製造方法を示
す工程図である。 1・・・・・・半導体基板、2,4・・・・・・酸化膜
、3・・・・・・多結晶シリコン膜、5・・・・・・導
電膜。
FIGS. 1(a) and 1(b) are process diagrams showing the manufacturing method of the present invention, and FIGS. 2(a) to (C) are process diagrams showing the manufacturing method according to the conventional method. 1... Semiconductor substrate, 2, 4... Oxide film, 3... Polycrystalline silicon film, 5... Conductive film.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に絶縁膜を介して第1の多結晶シリコン膜
を形成し、さらに連続してドーピングガスを導入しなが
ら第2の多結晶シリコン膜を形成する工程と、前記第1
、第2の多結晶シリコン層を選択的にエッチングしパタ
ーンを形成する工程と、前記第1、第2の多結晶シリコ
ン層をN_2雰囲気中で熱処理する工程を含むことを特
徴とする半導体装置の製造方法。
forming a first polycrystalline silicon film on a semiconductor substrate via an insulating film, and further forming a second polycrystalline silicon film while continuously introducing a doping gas;
, a step of selectively etching a second polycrystalline silicon layer to form a pattern; and a step of heat-treating the first and second polycrystalline silicon layers in an N_2 atmosphere. Production method.
JP17962789A 1989-07-11 1989-07-11 Manufacture of semiconductor device Pending JPH0344032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17962789A JPH0344032A (en) 1989-07-11 1989-07-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17962789A JPH0344032A (en) 1989-07-11 1989-07-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0344032A true JPH0344032A (en) 1991-02-25

Family

ID=16069074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17962789A Pending JPH0344032A (en) 1989-07-11 1989-07-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0344032A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825050A (en) * 1995-05-25 1998-10-20 Nec Corporation Thin film transistor having tapered active layer formed by controlling defect density and process of fabrication thereof
US6476496B1 (en) 1999-06-28 2002-11-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US6507072B2 (en) 1993-03-16 2003-01-14 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor device and forming method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6507072B2 (en) 1993-03-16 2003-01-14 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor device and forming method thereof
US5825050A (en) * 1995-05-25 1998-10-20 Nec Corporation Thin film transistor having tapered active layer formed by controlling defect density and process of fabrication thereof
US6476496B1 (en) 1999-06-28 2002-11-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
KR100371287B1 (en) * 1999-06-28 2003-02-06 미쓰비시덴키 가부시키가이샤 Semiconductor device and method of manufacturing the same

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