JPH0344889A - Refresh control circuit - Google Patents

Abstract

PURPOSE:To continuously attain the operation of a system even in the case of occurring a fault by using the refresh address outputted from an address counter thereafter when abnormality occurs on the refresh address outputted from address resister. CONSTITUTION:The address resister 1 fetches the refresh address 100 from an outer device, and outputs the refresh address 110 to a selector 3 and a checking circuit 4. The selector 3 supplies the refresh address 110 to a memory array 6 until the checking circuit 4 detects an error, and after detecting the error the refresh address 120 outputted from the address counter 2 is supplied to the memory array 6. At this time the refresh address 120 is the address fetching a first refresh address 100 and being updated, and is the same as the refresh address 100 in the case of the normal operation. In such a manner, even if the error is detected, the system can be operated without stopping the system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device that requires a refresh operation, and more particularly to a refresh control circuit that employs a row address strobe (RAS) only refresh method.

[Prior Art] Conventionally, in a storage device that performs a refresh operation using the RAS-only refresh method, the x1 timing and refresh address are determined using a dynamic memory element (D
RAM) and is controlled so that all refresh addresses go around within a predetermined time. In such storage devices, the normality of the refresh cycle and refresh address is important, and if an abnormality occurs in these.

Since the stored contents of memory elements cannot be guaranteed, checks such as refresh cycle monitoring and refresh address parity checks are performed.

[Problems to be Solved by the Invention] In the conventional storage device described above, if an abnormality occurs in, for example, a refresh address, a check circuit detects the error and reports the fault to a maintenance/diagnosis device or the like. The maintenance diagnostic equipment that received the fault report recognizes that a serious fault has occurred in the storage device.

The system was stopped.

An object of the present invention is to provide a refresh control circuit that can operate the system without stopping even if an error is detected in the refresh address check circuit.

[Means for Solving the Problems] A refresh control circuit according to the present invention controls the refresh operation of the RAS-only refresh method, and includes a timing circuit that inputs a refresh request that occurs at a constant cycle and outputs a RAS signal to a memory element. , an address register that takes in the refresh address, an address counter that takes in the refresh address when the set signal output by the timing circuit is on, and updates the counter value with a refresh request when the set signal is off, and an address register that takes in the refresh address. A check circuit that inspects the received refresh address and turns on an error signal when an abnormality is detected, selects the output of the address register when the error signal is off, and selects the output of the address counter when the error signal is on. and a selector that supplies a refresh address to the memory element.

[Example] Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing a refresh control circuit that receives a refresh request and a refresh address from an external device and performs a RAS-only refresh operation.

Address register 1 takes in refresh address 100 from an external device and outputs refresh address 110 to selector 3 and check circuit 4. The check circuit 4 checks the normality of the refresh address 110, and when detecting an abnormality, turns on the error signal 300 and maintains this state thereafter.

The timing circuit 5 receives the refresh request 200 as an input signal and outputs the RAS signal 401 to the memory array 6 composed of dynamic memory elements to start a RAS-only refresh operation. It also outputs a set signal 400 to the address counter 2, which is initially on and turns off when the first refresh request 200 is received.

The address counter 2 takes in the refresh address 100 when the set signal 400 is on and the refresh request 200 is received, and when the set signal 400 is off and the refresh request 200 is received, the address counter 2 increments the counter value by +1. That is, in the first refresh request 200, the refresh address 100 is fetched, and in the second and subsequent refresh requests 200, the fetched refresh address 100 is updated by adding +1, and the refresh address 120 is output.

The selector 3 receives the error signal 3 output from the check circuit 4.
The operation is as follows depending on the state of 00.

When error signal 300 is off, refresh address 110 from address register 1 is selected.

When error signal 300 is on, refresh address 120 from address counter 2 is selected and refresh address 130 is supplied to memory array 6. That is, until the check circuit 4 detects an error, the refresh address 110 output from the address register 1 is supplied to the memory array 6, and after the error is detected, the refresh address 120 output from the address counter 2 is supplied to the memory array 6. At this time, refresh address 12
0 is an address obtained by fetching and updating the first refresh address 100, and is the same as the refresh address 110 when operating normally.

[Effects of the Invention] As explained above, the refresh control circuit of the present invention has
While operating under normal conditions, the refresh address output by the address register is used, and if an error occurs in this refresh address, the refresh address output by the address counter is used from then on.
It is possible to provide a normal refresh address to the memory array. Therefore, unlike the conventional system, there is no need to immediately stop the system, and even if there is a failure, the system can be operated continuously, contributing to improved system reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a storage device including a refresh control circuit according to an embodiment of the present invention. 1...Address register, 2...Address counter. 3... Selector, 4... Check circuit, 5... Timing circuit, 6... Memory array.

Claims (1)

[Claims] 1. In a memory device that receives a refresh request and refresh address from an external device and performs a refresh operation using the row address strobe-only refresh method, a refresh request that occurs at a constant cycle is input, and a row address strobe signal is sent to the memory element. an address register that takes in an input refresh address generated in synchronization with the refresh request and outputs a first refresh address; and a timing circuit that outputs a first refresh address when the set signal is on; An address counter that takes in an address, updates a counter value according to the refresh request when the set signal is off, and outputs a second refresh address, and checks the first refresh address and turns on an error signal when an abnormality is detected. a check circuit that selects the first refresh address when the error signal is off, selects the second refresh address when the error signal is on, and outputs the selected refresh address to the memory element. A refresh control circuit comprising a selector.