JPH0345410B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a bus system for a service processor connected to a main unit of an information processing apparatus through a common bus.

Prior Art and Problems It is well known that a service processor (SVP) is attached to the main unit of an information processing device and is assigned to perform various tasks such as failure diagnosis. this
Conventionally, access to the main unit from the SVP has been a direct method, which has the advantage of being able to execute the task immediately without waiting, but if the task takes a long time to execute, the main unit
There is a problem in that the bus between SVPs is occupied for a long time, and during that time the operation of other devices connected to the bus, such as main memory, I/O, etc., is hindered.

To explain this with reference to the drawings, in FIG. 1, 10 is a service processor, 12 is a main unit, and B is a bus connecting these. 14 is an interface device inserted between the bus B and the main device 12, which includes a control circuit.
CNT, select address register SAR, output data register ODR, input data register IDR,
Equipped with selector SEL. When SVP loads data to the main unit, it uses read/write (read/write).
Put the data write on the R/W (Write) line (R/W
For example, set the line to H (high) level to indicate data write), address bus (1 byte)
The address of the register of the main unit to be loaded is placed on AB (the address is set in SAR), and the data to be loaded is placed on the data bus (2 bytes) DB (the data is set in ODR). In FIG. 1a, the above-mentioned relevant portions are indicated by thick lines.

An access pulse line AP and a byte select line are connected between the interface device 14 and the main device 12.
BS, register select line (1 byte) RS, load data line (1 byte) LD, sense data line (1 byte) SD are provided, and the control circuit
When the CNT is instructed to load data by the R/W line, it starts the counter CTR and notifies the main unit through the BS line that the first byte is 0 and the next byte 1, and also operates the selector SEL. The 0th byte and 1st byte of each data of the ODR are selected, and an access pulse is sent through the AP line to cause the main unit 12 to take in the ODR data to the register at the specified address. The portions corresponding to the above are shown in bold lines in FIG. 1b. Note that in other figures, the thick lines indicate the corresponding parts.

The control circuit CNT increments the counter CTR and sends the 0th byte and 1st byte data to the main unit, and then returns ACK to the SVP through the acknowledgment line ACK, as shown in Figure 1c.
Transfer of 2-byte data from to the main unit is completed.
If there is next data to be transferred, the same process will be repeated,
If not, SVP releases bus B.

In this way, when loading data to the main unit, SVP must load data through the R/W line, AB line, and DB line, the address of the register of the main unit to be loaded is ××, and the load data is × After instructing that ×, the control circuit
It is in the WAIT state waiting for a response until an ACK is returned from CNT, and has exclusive use of bus B.

The same goes for reading data from the main unit to the SVP; in this case, the SVP instructs the read using the R/W line, puts the address of the register of the main unit 12 to be read on the AB line, and reads this into the SAR. The control circuit CNT of the interface device 14 starts the counter CTR and initially sets it to 0 through the BS line.
Instructs the th data and places an access pulse on the AD line. In response to this access pulse, the main unit 12 takes in the data on the BS line and the RS line, and sends the 0th data (1 byte) of the register at the specified address to the input data register IDR through the SD line. The counter CTR of the control circuit CNT increments and then indicates the first data, and the main unit reads the BS line with the access pulse and sends the first data to the register IDR. Next is the control circuit CNT
sends the 2-byte data in register IDR to SVP through the DB line, and returns ACK through the ACK line. SVP exclusively uses bus B until this ACK is returned. Bus B is a common bus that is also used by other devices.

Purpose of the Invention The present invention improves the above points, so that the SVP requests processing to the interface device and entrusts the execution of the processing to the interface device, and the SVP immediately releases the bus and It is intended to enable the conventional direct processing method as well as the indirect processing method, thereby improving the overall throughput and shortening the processing waiting time.

Composition of the Invention The present invention provides a mode instruction signal sent from the service processor to a control circuit of the interface device in a bus system in which a service processor is connected to a main unit of an information processing device through a common bus and an interface device. Accordingly, when the service processor is in the direct mode that directly accesses the main device, an acknowledgment is returned upon completion of the access, and when the interface device is in the indirect mode that accesses the main device on behalf of the service processor, the access request is returned. The service processor is characterized in that it has a function of returning an acknowledgment at the stage of acceptance, and the service processor is able to open the common bus when the acknowledgment is returned.This will be explained below with reference to an embodiment. do.

Embodiment of the Invention FIG. 2 shows an embodiment of the invention, in which the same parts as in FIG. 1 are given the same reference numerals. As is clear from comparing the two, in Figure 2, the control circuit CNT
There is an AB line, which indicates direct mode or indirect mode. Further, a selector SEL is provided on the input side of the select address register SAR, and switches the input line to the register SAL to the AB line or the DB line. In addition to the register select signal RS, the register SAR can be loaded (L) or sensed (S).
It generates a signal indicating what to do. Further output register
Both ODR and input register IDR have a capacity of 4 bytes. SAR, AB, LD, SD each 1 byte, DB
is 2 bytes. This device is capable of data transfer in direct mode and data transfer in indirect mode, which will now be described with reference to FIGS. 3 to 6.

First, to explain indirect data loading, as shown in Figure 3a, SVP stores 4-byte load data into register ODR through the DB line. This is executed by indicating to CNT that this is the first or second access to ODR and instructing write (W) using the R/W line. When this process is completed, control circuit CNT returns ACK to SVP.

Next, as shown in Figure 3b, the SVP places the address of the register of the main unit to be loaded and a bit indicating that it is a load on the DB line, and sends an indirect mode signal and a select operation signal (SAR input side) to the AB line. signal that causes the selector SEL to select the DB line)
The SAR is loaded with data on the DB line, and the R/W line is used to instruct the SAR to write. Upon receiving this, the control circuit CNT returns ACK and main unit 1
Start data transfer to 2. Since ACK is returned, SVP releases the bus. This state is shown in Figure 3c.
Shown below. When the bus is released, SVP goes into standby mode, but
Of course, at this time, access to the main device must not be restarted. This access prohibition process is performed by time monitoring using the SVP software. The data transfer is performed four times, one byte at a time, and the counter CTR of the control circuit CNT indicates the number of transfers. That is, at the start of transfer, the counter CTR of the control circuit starts operating, and notifies the main unit of the count value through the BS line, and operates the ODR output side selector SEL. Being a data load
The address of the data storage register is notified from the SAR to the main unit through the L/S line, the address of the data storage register is notified from the SAR through the RS line, the access pulse that becomes the strobe signal is sent through the AP line each time, and the load data is sent one byte at a time through the LD line. Sent to the main unit.

Next, to explain indirect sensing operation with reference to Figure 4, in this case, SVP puts the address of the register of the main unit to be read and a signal indicating sensing on the DB line, and operates a selector on the AB line. A signal and an indirect mode signal are loaded to instruct the control circuit CNT to perform a sensing operation. When receiving this, the control circuit
CNT returns ACK, and SVP releases bus B.
This state is shown in FIG. 4b. Even if the SVP releases the bus, it cannot access the main device 12 for a predetermined period of time, as in the case of loading. The control circuit CNT activates the counter CTR to instruct how many times the data is received this time, thereby switching the selector SEL on the input side of the input data register IDR, and SAR selects the main body to be accessed that was previously received from SVP. The device's register address and a bit indicating sense are sent back to the BS and RS lines. The main unit receives these APs and the AP from the CNT, and transmits the contents of the accessed register 1 byte at a time through the SD line four times. This is sequentially switched by selector SEL.
Sequentially packed into byte register IDR.

The 4-byte data taken into the input register IDR is taken into the SVP in two parts of 2 bytes each through the DB line. This is shown in Figure 4c. In other words, after a predetermined time, SVP secures bus B and registers it on the AB line.
Load the IDR address (a signal indicating how many times the data has been taken in) and instruct reading using the R/W line. As a result, the control circuit 14 operates the selector SEL on the output side of the register IDR, and places the data of the designated register address on the DB line. SVP takes this in, specifies the next register address, and receives that data as well. In this way, the 4-byte data in the register IDR is acquired by transferring 2 bytes twice. When this process is completed, the control circuit CNT returns ACK.

Next, to explain data loading in direct mode with reference to Figure 5, in this case the SVP is 2.
Put the byte load data on the DB line, put the register address of the main unit to be loaded, the direct mode signal, and the selector operation signal on the AB line,
Instruct writing using the R/W line. This is the state shown in FIG. 5a. The select address register SAR stores the address of the register of the main unit and a signal indicating write, and the output register ODR stores 2-byte data to be loaded.

When the control circuit is instructed to perform a write operation in the direct mode as described above, it starts the counter CTR as shown in Figure 5b, instructs the number of bytes of data to be transferred, and also performs access control. Sends pulse AP, and register SAR instructs register address and load. As a result, the main device takes in the 2-byte data of the ODR one byte at a time into the register specified by the address and byte select BS. When this is completed, the control circuit CNT returns ACK to SVP as shown in FIG. 5c. This completes loading the 2-byte data, and if there is no remaining load data, SVP releases bus B. Until this bus is released, the bus is in exclusive use.

The sensing operation in direct mode is performed as shown in FIG. That is, as shown in FIG. 6a, the SVP places the register address of the main unit to be read, a direct mode signal, and a selector operation signal on the AB line, and also puts a read signal on the R/W line. The register address and read signal of the main unit are stored in the select address register SAR.

When the control circuit CNT is instructed to sense the direct mode, it starts the counter CTR, places the access count on the BS line, puts an access pulse on the AP line, and registers the register SAR, as shown in Figure 6b. places the address of the register accessing the RS line and a signal indicating a sense operation on the L/S line. As a result, the main unit sends the data of the specified register twice, 1 byte each, through the SD line, and this is the input data register IDR.
be taken into. When data is stored in register IDR, the data appears on the DB line, so SVP
Import data from DB line. When this operation is completed, as shown in FIG. 6c, the control circuit CNT sends an ACK, and if there is no data to be sensed next, the SVP releases the bus and ends the sensing operation.

The control circuit CNT sends the byte select BS signal and the access pulse AP serving as a strobe to the main unit 12 as described above, and also sends the registers ODR,
The IDR and selector SEL are operated and controlled, and these are reprinted in FIGS. 7 and 8. Although not shown in the previous figure, the control circuit CNT is a decoder.
A DBC is also provided, and this decoder decodes the AB line to distinguish between direct/indirect mode and control access to ODR. Further, a strobe signal STR is input from the SVP 10, and in response to this, the counter CTR starts stage counting and byte counting. The stage count is cleared every time a 1-byte main unit is accessed and is
The byte count is a clock counter that repeats 0 to 5 as shown in FIG. 0 and 1 are repeated in direct mode, and 0 to 3 are repeated in indirect mode. As shown in Figure 8b, when the strobe STR is input from SVP, address decoding is performed in the decoder DEC, stage count SC and byte count BC start,
Access pulse AP occurs. CE in Figure 7 is the clock enable, registers SAR, ODR,
Controls IDR data input/output.

As shown in Figure 8c, 0 to 5 of 8 bits 0 to 7 of the address bus are to be decoded, and as shown in Figure 8d, direct access and writing of data bus DB to SAR (indirect access) ), ODR
Writes to/reads to IDR are decoded. Whether or not it is an indirect access may be determined by providing one bit for that purpose, but in this example, it is notified by whether or not the above-mentioned "write to SAR" is obtained as a decoded output. In addition, this decoded output can be used as a switching signal for the selector SEL on the SAR input side. In this case, as shown in Figure 7, the operation signal line between AB and SEL is cut off (indicated by an x mark) and SEL,
Connect the DEC as shown by the dotted line.
The first bit 0 of the data stored in the select address register SAR is a bit indicating load/sense, and the remaining 1 to 7 bits are the address of the register of the main unit to be accessed. The 7th bit 6 of address bus AB is BS during direct access.
becomes 1 bit.

When loading data in direct mode, the control circuit CNT writes the contents of AB to SAR and the contents of DB to the upper or lower half of ODR, and BS is 0 or 2.
, create and output an AP with CTR, set BS to 1 or 3, output AP, and return ACK to SVP. Also, when sensing data in direct mode,
Write the contents of AB to SAR, set BS to 0 or 2, output AP, write sense data to 0 or 2 bytes of IDR, write sense data to 1 or 3 bytes in the same way, and select the output selector of IDR. selects 2 bytes and returns ACK to SVP. Next, when loading data in indirect mode, assume that the data is set in ODR, write the DB contents to SAR, and write the DB contents to SVP.
Returning ACK and increasing BS from 0 to 3
Issue AP. Furthermore, when sensing data in indirect mode, the contents of the DB are written to SAR and an ACK is returned to SVP. While the BS is up, the AP is sent out to obtain sense data, and it is stored in the IDR one byte at a time.

Effects of the Invention As explained above, in the present invention, the common bus is
When it is necessary to shorten the time occupied by SVP and improve throughput, access to the main device can be performed in indirect mode, and when continuous data transfer with the main device is required to simplify processing, direct mode can be adopted. This enables proper and efficient access to the main unit.

[Brief explanation of drawings]

Figure 1 is a block diagram explaining the conventional SVP bus system, Figures 2 to 6 are block diagrams explaining the SVP bus system of the present invention, and Figures 7 and 8 are diagrams explaining the interface section thereof. It is. In the drawing, B is a common bus, 14 is an interface device, 10 is a service processor, 12 is a main unit, CNT is a control circuit, and ACK is an acknowledgment.

Claims (1)

[Claims] 1. In a bus system in which a service processor is connected to a main unit of an information processing device through a common bus and an interface device, a mode instruction signal sent from the service processor to a control circuit of the interface device. Accordingly, when the service processor is in the direct mode that directly accesses the main device, an acknowledgment is returned upon completion of the access, and when the interface device is in the indirect mode that accesses the main device on behalf of the service processor, the access request is returned. A bus system for a service processor, characterized in that the service processor has a function of returning an acknowledgment at the stage of acceptance, and the service processor is able to open a common bus when the acknowledgment is returned.