JPH034544A - Position recognition pattern - Google Patents

Position recognition pattern

Info

Publication number
JPH034544A
JPH034544A JP1140207A JP14020789A JPH034544A JP H034544 A JPH034544 A JP H034544A JP 1140207 A JP1140207 A JP 1140207A JP 14020789 A JP14020789 A JP 14020789A JP H034544 A JPH034544 A JP H034544A
Authority
JP
Japan
Prior art keywords
recognition
chip
pattern
marks
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1140207A
Other languages
Japanese (ja)
Other versions
JP2674212B2 (en
Inventor
Toshio Suzuki
俊夫 鈴木
Yutaka Fujimoto
裕 藤本
Katsumi Ishikawa
克己 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP1140207A priority Critical patent/JP2674212B2/en
Publication of JPH034544A publication Critical patent/JPH034544A/en
Application granted granted Critical
Publication of JP2674212B2 publication Critical patent/JP2674212B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification
    • H10W46/601Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/603Formed on wafers or substrates before dicing and remaining on chips after dicing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07521Aligning
    • H10W72/07523Active alignment, e.g. using optical alignment using marks or sensors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To judge the positional relation between semiconductor chips by a position recognition pattern and to enhance a recognition accuracy by a method wherein recognition marks are respectively arranged at the corner parts of the chip by which the opposite angles of a quadrangular semiconductor chip are formed. CONSTITUTION:Recognition marks 12a and 12b are respectively arranged at the corner parts, by which the opposite angles of a quadrangular semiconductor chip 11 are made, of the chip 11 and the marks 12a and 12b are formed into a quadrangular form and are arranged on the sides inner slightly from the outer peripheries L of the chip. An area with a feature is previously ready-stored in a memory as a reference pattern in a processing system 8, a position recognition pattern which is formed by the marks 12a and 12b of the chip 11 is read out by a camera 7 and the position recognition pattern detected by the processing system 8 is compared with the previously stored reference pattern. An area having most meeting points is recognized as a target pattern, the amount of the positional deviation of the center of the reference pattern from the center of the recognized pattern is read and the final wire bonding position is decided.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、自動ホンダ等に備えられるチップ位置認識
装置に係り、詳しくは、自動パターン認識別能により半
導体チップの位置関係を判断する際の位置認識パターン
に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a chip position recognition device installed in an automobile, etc., and more specifically, to a device for determining the positional relationship of semiconductor chips by automatic pattern recognition. It concerns location recognition patterns.

[従来技術] 従来、例えばパワートランジスタのアルミワイヤボンデ
ィング装置にはチップ位置を認識するための装置が備え
られている。即ち、半導体チップに形成されたマークに
よる位置認識パターンを読取り、チップの位置関係を知
ることによりチップに形成されたワイヤポンディングパ
ッドの位置を識別するものである。第2図〜第4図には
このチップに形成される位置認識パターンの一例を示し
、半導体チップ1上にマーク2,3.4a、4.bが配
置されている。又、第5図にはチップ位置認識装置5の
一例を示し、ライト6にてチップ1を照らすとともにカ
メラ(@像装置)7にてそのマークにより形成されるパ
ターンを読み出し、処理系8によりこのパターンと予め
記憶したパターンと比較することによりチップ1の位置
関係を判断するようになっている。尚、第2図〜第4図
において、9はポンディングパッドを示す。
[Prior Art] Conventionally, for example, an aluminum wire bonding apparatus for a power transistor is equipped with a device for recognizing a chip position. That is, by reading a position recognition pattern based on marks formed on a semiconductor chip and knowing the positional relationship of the chips, the position of a wire bonding pad formed on the chip is identified. 2 to 4 show examples of position recognition patterns formed on this chip, with marks 2, 3.4a, 4. b is placed. FIG. 5 shows an example of the chip position recognition device 5, in which a light 6 illuminates the chip 1, a camera (@image device) 7 reads out the pattern formed by the mark, and a processing system 8 reads out the pattern formed by the mark. The positional relationship of the chip 1 is determined by comparing the pattern with a pre-stored pattern. In addition, in FIGS. 2 to 4, 9 indicates a bonding pad.

[発明が解決しようとする課題] ところが、第2,3図に示す位置認識パターンはマーク
が1つであるために、又、第4図に示す位置認識パター
ンはマーク4a、4bが近い距離に配置されているため
、位置認識精度が悪かった。
[Problems to be Solved by the Invention] However, since the position recognition patterns shown in FIGS. 2 and 3 have only one mark, and the position recognition pattern shown in FIG. Because of the location, location recognition accuracy was poor.

この発明の目的は、認識精度を向上させることができる
位置認識パターンを提供することにある。
An object of the present invention is to provide a position recognition pattern that can improve recognition accuracy.

[課題を解決するための手段] この発明は、四角形の半導体チップに認識マークが形成
され、光学系により当該認識マークによる位置認識パタ
ーンを読取り、半導体チップの位置関係を判断するよう
にしたチップ位置認識精度において、 四角形の半導体チップの対角を成す各隅部に認識マーク
をそれぞれ配置し、かつ、その少なくともいずれか一方
の認識マークを四角形状としチップ外周辺から内側に配
置した位置認識パターンをその要旨とするものである。
[Means for Solving the Problems] The present invention provides a chip positioning system in which a recognition mark is formed on a rectangular semiconductor chip, and a position recognition pattern based on the recognition mark is read by an optical system to determine the positional relationship of the semiconductor chips. In terms of recognition accuracy, a position recognition pattern is used in which recognition marks are placed at each diagonal corner of a rectangular semiconductor chip, and at least one of the recognition marks is square shaped and placed inward from the outside periphery of the chip. This is the summary.

[作用] 四角形の半導体チップの対角を成す各隅部に認識マーク
がそれぞれ配置され、その少なくともいずれか一方の認
識マークが四角形状を成しチップ外周辺から内側に配置
される。そして、光学系によりこの認識マークによる位
置認識パターンが読取られて半導体チップの位置関係が
判断されることとなる。
[Operation] Recognition marks are arranged at each diagonal corner of a rectangular semiconductor chip, and at least one of the recognition marks has a rectangular shape and is arranged inward from the outer periphery of the chip. Then, the position recognition pattern based on this recognition mark is read by an optical system, and the positional relationship of the semiconductor chips is determined.

[実施例] 以下、この発明を自動ボンダに僅えられるチップ位置認
識装置に具体化した一実施例を図面に従って説明する。
[Embodiment] Hereinafter, an embodiment in which the present invention is embodied in a chip position recognition device that can be used in an automatic bonder will be described with reference to the drawings.

第1図には本実施例の半導体チップ11の平面図を示し
、パワートランジスタ等が形成された半導体チップ11
は正方形状に形成されている。半導体チップ11の表面
の大部分はアルミ電極が配設され、又、伯の部分は酸化
膜又は窒化膜又はポリイミド等の樹脂膜が配置されてい
る。2つの認識マーク12a、12bはそれぞれ長方形
状を成し、半導体チップ11の対角を成す各隅部(コー
ナ部)に配設されている。この認識マーク12a。
FIG. 1 shows a plan view of the semiconductor chip 11 of this embodiment, and the semiconductor chip 11 on which power transistors etc. are formed is shown.
is formed into a square shape. An aluminum electrode is disposed on most of the surface of the semiconductor chip 11, and an oxide film, a nitride film, or a resin film such as polyimide is disposed on the circled portion. The two recognition marks 12a and 12b each have a rectangular shape, and are arranged at each diagonal corner (corner) of the semiconductor chip 11. This recognition mark 12a.

12bの配設位置は、半導体チップ11の外周辺りから
僅かに(距離二j)内側に入った所であり、かつ、認識
マーク12a、12bの長手方向が半導体チップ11の
中心に向かうように配置されている。
The arrangement position of the recognition marks 12b is slightly (distance 2j) inward from the outer periphery of the semiconductor chip 11, and is arranged so that the longitudinal direction of the recognition marks 12a and 12b is directed toward the center of the semiconductor chip 11. has been done.

このマーク領域内はアルミが無く表面が酸化膜(又は、
窒化膜あるいは樹脂膜)となっており、半導体チップ1
1表面の大部分がアルミ電極であるために白色であり、
認識マーク12a、12bよりなる位置認識パターンは
黒っぽく見える。このようにチップ表面に白黒のコン1
〜ラストができる。
There is no aluminum in this mark area, and the surface is covered with an oxide film (or
(nitride film or resin film), and the semiconductor chip 1
1 Most of the surface is white because it is made of aluminum electrodes,
The position recognition pattern made up of the recognition marks 12a and 12b appears blackish. In this way, a black and white controller 1 is placed on the chip surface.
~I can do the last one.

尚、このマーク12a、12bの形成は、組立て工程(
後工程)に入る前のチップをウェハ内に作るウェハ工程
(前工程)で行なわれるものである。
The marks 12a and 12b are formed during the assembly process (
This is done in the wafer process (pre-process) where chips are made on the wafer before entering the post-process.

そして、第5図のチップ位置認識装置5により半導体チ
ップ11の位置認識が行なわれる。つまり、コンピュー
タを含んだ処理系8において特徴のあるエリアを予め標
準パターンとしメモリに記憶しておき、カメラ(撮像装
置)7にて半導体チップ11の認識マーク12a、12
bにより形成される位置認識パターンを読み出し、処理
系8により、検出された位置認識パターンと予めメモリ
に記憶された標準パターンとが比較される。そして、最
も一致点の多いエリアを目標パターンとして認識して、
標準パターン中心と認識した(検出した)パターンの中
心との位置ズレ量が読取られて最終的なワイヤボンディ
ング位置が決定される。
Then, the position of the semiconductor chip 11 is recognized by the chip position recognition device 5 shown in FIG. That is, in the processing system 8 including the computer, a characteristic area is made into a standard pattern and stored in memory in advance, and the recognition marks 12a, 12 of the semiconductor chip 11 are used with the camera (imaging device) 7.
The position recognition pattern formed by b is read out, and the processing system 8 compares the detected position recognition pattern with a standard pattern previously stored in the memory. Then, the area with the most matching points is recognized as the target pattern, and
The amount of positional deviation between the center of the standard pattern and the center of the recognized (detected) pattern is read to determine the final wire bonding position.

その後、所定の位置へのワイヤボンディングが行なわれ
る。
Thereafter, wire bonding to a predetermined position is performed.

このように本実施例では、四角形の半導体チップ11の
対角を成す各隅部に認識マーク12a。
As described above, in this embodiment, recognition marks 12a are provided at each diagonal corner of the rectangular semiconductor chip 11.

12bをそれぞれ配置し、かつ、その認識マーク12a
、12bを四角形状(長方形)としチップ外周辺りから
僅かに内側に配置した。その結果、認識マークを2つと
し、又、認識マークをデツプ11上で最も離間する対角
位置に配置したので、認識精度を向上させることができ
ることとなる。
12b, and their recognition marks 12a.
, 12b had a square shape (rectangle) and were arranged slightly inside from the outer periphery of the chip. As a result, since there are two recognition marks and the recognition marks are placed at the farthest diagonal positions on the depth 11, recognition accuracy can be improved.

又、パターン認識の際に、第6図に示すようにマーク1
3a、13bがfLJ字状のものでは第7図に示すよう
にチップ1の周辺のスクライブライン(スクライブパタ
ーン)14や第8図に示すようなチップマウン1〜材の
はみ出し部15を位置認識パターンとして誤認識してし
まう虞がある。
Also, during pattern recognition, as shown in Figure 6, mark 1
3a and 13b are fLJ-shaped, the scribe line (scribe pattern) 14 around the chip 1 as shown in FIG. 7 and the protruding portion 15 of the chip mount 1 to the material as shown in FIG. There is a risk of misunderstanding.

しかしながら、本実施例のようにマークを四角形状とし
、かつ、例えば第1図の12a、12bのような配置に
することにより、チップスクライブライン14やデツプ
下からはみ出したチップマウント材(第8図のはみ出し
部15)やチップの影等を位置認識パターンとして誤認
識することが回避される。
However, as in this embodiment, by making the marks square and arranging them as shown in 12a and 12b in FIG. This prevents erroneous recognition of the protruding portion 15), the shadow of the chip, etc. as a position recognition pattern.

尚、この発明は上記実施例に限定されるものではなく、
例えば、認識マークは長方形の他にも正方形であっても
よく、ざらに、認識マーク12a。
Note that this invention is not limited to the above embodiments,
For example, the recognition mark may be a square instead of a rectangle, roughly the recognition mark 12a.

12bの隅部を円弧形状としたり所定の角度に切り欠い
てもよい。
The corners of 12b may be formed into an arc shape or may be cut out at a predetermined angle.

さらに、半導体チップ11の対角に配置するマークは、
いずれか一方の認識マークを四角形状としチップ外周辺
りから内側に配置すればよく、片方のマークを四角形状
以外の形状としてもよい。
Furthermore, the marks placed diagonally on the semiconductor chip 11 are
Either one of the recognition marks may have a rectangular shape and be placed inward from the outer periphery of the chip, or one of the marks may have a shape other than the rectangular shape.

即ら、例えば、片方のマークとして、半導体チップの隅
部に設けられ、レイアウト設計上の半導体チップのアル
ミ電極の有無による白黒のコントラスト部を使用しても
よい。
That is, for example, as one of the marks, a black and white contrast portion provided at a corner of the semiconductor chip and depending on the presence or absence of an aluminum electrode on the semiconductor chip in layout design may be used.

[発明の効果] 以上詳述したようにこの発明によれば、認識精度を向上
させることができる優れた効果を発揮する。
[Effects of the Invention] As described in detail above, the present invention exhibits an excellent effect of improving recognition accuracy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は実施例の半導体チップの平面図、第2図は従来
技術を説明するための半導体チップの平面図、第3図は
従来技術を説明するための半導体チップの平面図、第4
図は従来技術を説明するための半導体チップの平面図、
第5図は認識装置を示す概略図、第6図は比較のための
半導体チップの平面図、第7図は比較のための半導体チ
ップの平面図、第8図は比較のための半導体チップの平
面図である。 5はチップ位防認識装置、6はライト、7はカメラ、8
は処理系、11は半導体チップ、12aは認識マーク、
12bは認識マーク、しは外周辺。
FIG. 1 is a plan view of a semiconductor chip according to an embodiment, FIG. 2 is a plan view of a semiconductor chip for explaining a conventional technique, FIG. 3 is a plan view of a semiconductor chip for explaining a conventional technique, and FIG.
The figure is a plan view of a semiconductor chip to explain the conventional technology.
FIG. 5 is a schematic diagram showing a recognition device, FIG. 6 is a plan view of a semiconductor chip for comparison, FIG. 7 is a plan view of a semiconductor chip for comparison, and FIG. 8 is a plan view of a semiconductor chip for comparison. FIG. 5 is a chip level recognition device, 6 is a light, 7 is a camera, 8
is a processing system, 11 is a semiconductor chip, 12a is a recognition mark,
12b is the recognition mark, and shi is the outer periphery.

Claims (1)

【特許請求の範囲】[Claims] 1、四角形の半導体チップに認識マークが形成され、光
学系により当該認識マークによる位置認識パターンを読
取り、半導体チップの位置関係を判断するようにしたチ
ップ位置認識装置において、四角形の半導体チップの対
角を成す各隅部に認識マークをそれぞれ配置し、かつ、
その少なくともいずれか一方の認識マークを四角形状と
しチップ外周辺から内側に配置したことを特徴とする位
置認識パターン。
1. In a chip position recognition device in which a recognition mark is formed on a rectangular semiconductor chip, and an optical system reads the position recognition pattern formed by the recognition mark to determine the positional relationship of the semiconductor chips, the diagonal of the rectangular semiconductor chip is used. A recognition mark is placed at each corner of the
A position recognition pattern characterized in that at least one of the recognition marks has a rectangular shape and is arranged inward from the outer periphery of the chip.
JP1140207A 1989-05-31 1989-05-31 Position recognition pattern Expired - Lifetime JP2674212B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1140207A JP2674212B2 (en) 1989-05-31 1989-05-31 Position recognition pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1140207A JP2674212B2 (en) 1989-05-31 1989-05-31 Position recognition pattern

Publications (2)

Publication Number Publication Date
JPH034544A true JPH034544A (en) 1991-01-10
JP2674212B2 JP2674212B2 (en) 1997-11-12

Family

ID=15263411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1140207A Expired - Lifetime JP2674212B2 (en) 1989-05-31 1989-05-31 Position recognition pattern

Country Status (1)

Country Link
JP (1) JP2674212B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741653U (en) * 1980-08-20 1982-03-06
JPS5881938U (en) * 1981-11-26 1983-06-03 日本電気ホームエレクトロニクス株式会社 semiconductor equipment
JPS63185233U (en) * 1987-05-21 1988-11-29

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741653U (en) * 1980-08-20 1982-03-06
JPS5881938U (en) * 1981-11-26 1983-06-03 日本電気ホームエレクトロニクス株式会社 semiconductor equipment
JPS63185233U (en) * 1987-05-21 1988-11-29

Also Published As

Publication number Publication date
JP2674212B2 (en) 1997-11-12

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