JPH034585A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH034585A JPH034585A JP1140469A JP14046989A JPH034585A JP H034585 A JPH034585 A JP H034585A JP 1140469 A JP1140469 A JP 1140469A JP 14046989 A JP14046989 A JP 14046989A JP H034585 A JPH034585 A JP H034585A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- printed
- integrated circuit
- insulating layer
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明はテレビ、VTR、オーディオ機器等の電子通信
機器の電気回路に使用することのできる混成集積回路装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a hybrid integrated circuit device that can be used in electrical circuits of electronic communication equipment such as televisions, VTRs, and audio equipment.
従来の技術
従来より、混成集積回路装置の実装密度を高める手段と
して印刷抵抗を用いている。この場合、印刷抵抗は単層
又は多層の層毎に形成している。BACKGROUND OF THE INVENTION Printed resistors have traditionally been used as a means of increasing the packaging density of hybrid integrated circuit devices. In this case, the printed resistor is formed for each single layer or multiple layers.
従来例を第5図、第6図に示す、第5図は従来の混成集
積回路装置の単層の場合の例で、同図(a)は抵抗体部
分の断面図、同図(ロ)は同斜視図を表わし、第6図は
従来の混成集積回路装置の多層の場合の例で抵抗体部分
の断面図を表わす。Conventional examples are shown in Figs. 5 and 6. Fig. 5 is an example of a single layer of a conventional hybrid integrated circuit device, and Fig. 5 (a) is a cross-sectional view of the resistor portion, and Fig. 5 (b) is a cross-sectional view of the resistor portion. 6 shows a perspective view of the same, and FIG. 6 shows a cross-sectional view of a resistor portion in an example of a multilayer conventional hybrid integrated circuit device.
第5図および第6図において、21.22は単層の印刷
抵抗体、23は導体、24は基板、25は多層の下層印
刷抵抗体、26は絶縁層、27は多層の上層印刷抵抗体
、28はトリミング溝である。5 and 6, 21 and 22 are single-layer printed resistors, 23 is a conductor, 24 is a substrate, 25 is a multilayer lower layer printed resistor, 26 is an insulating layer, and 27 is a multilayer upper layer printed resistor. , 28 are trimming grooves.
発明が解決しようとする課題
しかしながら上記従来例では、
(1)印刷抵抗の占有面積は各本体の面積及びトリミン
グ等のためのデッドスペースの合計だけ必要で実装密度
を高める上での障害となる。Problems to be Solved by the Invention However, in the conventional example described above, (1) the area occupied by the printed resistor is the sum of the area of each main body and the dead space for trimming, etc., which is an obstacle to increasing the packaging density.
(2)多層の場合に限り
(a)トリミング時に絶縁層26が破壊して抵抗値に悪
影響を及ぼす。(2) Only in the case of multiple layers (a) The insulating layer 26 is destroyed during trimming, which adversely affects the resistance value.
[有])絶縁層26は数10u−と薄く、その下に導体
等があるとトリミング時に損傷を与える恐れがある。The insulating layer 26 is as thin as several tens of microns, and if there is a conductor or the like underneath it, there is a risk of damage during trimming.
(C) 各層毎に抵抗トリミング工程があり工数が多
くなる。(C) There is a resistor trimming process for each layer, which increases the number of man-hours.
(d) 下層の抵抗体をトリミングした後に絶縁層形
成等の熱処理があり最終的な抵抗値の制御が難しい等の
問題点がある。(d) After trimming the lower layer resistor, heat treatment such as forming an insulating layer is required, and there are problems such as difficulty in controlling the final resistance value.
本発明は前記問題点に鑑み、実装密度を高め、印刷抵抗
を精度良(作り、工数を削減する混成集積回路装置を提
供することを目的とるすものである。SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a hybrid integrated circuit device that increases packaging density, produces printed resistors with high precision, and reduces man-hours.
課題を解決するための手段
上記の問題点を解決するめための本発明の混成集積回路
装置は、ホーロー基板上に、酸化ルテニューム系印刷抵
抗を形成し、前記印刷抵抗体の一部分上に無機ガラス系
又は有機系絶縁層を形成し、前記絶縁層上に、前記印刷
抵抗とクロスオーバーして、酸化ルテニュームあるいは
有機系の印刷抵抗体を形成したものである。Means for Solving the Problems In order to solve the above-mentioned problems, a hybrid integrated circuit device of the present invention includes forming a printed resistor based on ruthenium oxide on a hollow substrate, and forming an inorganic glass based printed resistor on a portion of the printed resistor. Alternatively, an organic insulating layer is formed, and a ruthenium oxide or organic printed resistor is formed on the insulating layer to cross over with the printed resistor.
作用
本発明は上記の構成により、印刷抵抗の占有面積を減ら
し、実装密度を高めることができる。また印刷抵抗のト
リミングは全て、ホーロー基板上で行ない、且つ、最後
に一括して行えるため、抵抗値の精度が従来例では5%
〜10%のバラツキがあるのに対し、本発明では1%以
下にすることが可能である。さらに、トリミングの工数
を減らすことができるものである。Function: With the above configuration, the present invention can reduce the area occupied by the printed resistor and increase the packaging density. In addition, all the trimming of the printed resistors is done on the enamel board and all at once at the end, so the accuracy of the resistance value is 5% compared to the conventional example.
While there is a variation of ~10%, the present invention can reduce the variation to 1% or less. Furthermore, the number of man-hours for trimming can be reduced.
実施例
以下、本発明の一実施例の混成集積回路装置について図
面を参照しながら説明する。第1図は本発明の第1の実
施例における混成集積回路装置の印刷抵抗部分の断面図
、第2図は同じく印刷抵抗部分の斜視図を示す。Embodiment Hereinafter, a hybrid integrated circuit device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a printed resistor portion of a hybrid integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a perspective view of the same printed resistor portion.
第1図、第2図において、1は下層の酸化ルテニューム
系の抵抗体、2は硼珪酸ガラス等の無機ガラス系絶縁層
、3は酸化ルテニューム系印刷抵抗1とクロスオーバー
する酸化ルテニューム系印刷抵抗体、4はAg、/Pd
等の導体、5はホーロー基板、6はトリミング溝である
。In Figures 1 and 2, 1 is a lower layer ruthenium oxide resistor, 2 is an inorganic glass insulating layer such as borosilicate glass, and 3 is a ruthenium oxide printed resistor that crosses over with the ruthenium oxide printed resistor 1. body, 4 is Ag, /Pd
5 is a hollow substrate, and 6 is a trimming groove.
上記の構成要素を存する混成集積回路装置の形成方法に
ついて以下説明する。酸化ルテニュームを主成分とする
印刷抵抗体1を基板5上に印刷、乾燥後850°C前後
の温度で空気雰囲気中で焼成する。その後の無機ガラス
系の絶縁層2を印刷抵抗体lの上に印刷乾燥し、そして
850℃前後の温度で空気雰囲気中で焼成する。その後
、印刷抵抗体lとは絶縁層2で電気的に絶縁され、印刷
抵抗体1とクロスオーバーする酸化ルテニューム系の印
刷抵抗体3を印刷、乾燥したのち850℃前後の温度で
空気雰囲気中で焼成し形成する。このようにして絶縁層
2で電気的に絶縁された重なり合う印刷抵抗体1.3を
形成する。抵抗のトリミングはその後−括して行なう。A method of forming a hybrid integrated circuit device including the above-mentioned components will be described below. A printed resistor 1 containing ruthenium oxide as a main component is printed on a substrate 5, dried, and then fired in an air atmosphere at a temperature of about 850°C. Thereafter, an inorganic glass-based insulating layer 2 is printed and dried on the printed resistor l and fired in an air atmosphere at a temperature of around 850°C. Thereafter, a printed resistor 3 of ruthenium oxide, which is electrically insulated from the printed resistor 1 by an insulating layer 2 and crosses over with the printed resistor 1, is printed and dried in an air atmosphere at a temperature of around 850°C. Fire and form. In this way, overlapping printed resistors 1.3 are formed which are electrically insulated by the insulating layer 2. Trimming of the resistors is then done collectively.
ちなみにAg/Pd等の導体4は下層印刷抵抗体1の形
成前に形成しておく。Incidentally, the conductor 4, such as Ag/Pd, is formed before the lower printed resistor 1 is formed.
以上のように実施例によれば、下層抵抗体1の一部分を
絶縁層2で覆い、その絶縁112上で上層抵抗体3を下
層抵抗体1にクロスオーバーし形成することにより、実
装密度を高め、抵抗を精度良くトリミングしトリミング
工数を減らすことができる。As described above, according to the embodiment, a part of the lower resistor 1 is covered with the insulating layer 2, and the upper resistor 3 is formed by crossing over to the lower resistor 1 on the insulation 112, thereby increasing the packaging density. , the resistor can be trimmed with high precision and the number of trimming steps can be reduced.
第3図は本発明の第2の実施例における混成集積回路装
置の印刷抵抗部分の断面図、第4図は同じく印刷抵抗部
分の斜視図を示す。FIG. 3 is a sectional view of a printed resistor portion of a hybrid integrated circuit device according to a second embodiment of the present invention, and FIG. 4 is a perspective view of the same printed resistor portion.
第3図、第4図において1.4〜6は第1図、第2図と
同様に、各々、1は下層の酸化ルテニューム系印刷抵抗
体、4はAg/pd等の導体、5はホーロー基板、6は
トリミング溝を表す。11はエポキシ樹脂等の有機系絶
縁層、12はカーボン等を主成分とする有機系印刷抵抗
体である。In Figures 3 and 4, 1.4 to 6 are the same as in Figures 1 and 2, respectively, 1 is the lower layer ruthenium oxide printed resistor, 4 is a conductor such as Ag/PD, and 5 is enamel. On the substrate, 6 represents a trimming groove. 11 is an organic insulating layer made of epoxy resin or the like, and 12 is an organic printed resistor whose main component is carbon or the like.
酸化ルテニューム系の印刷抵抗体1を印刷、乾燥後、8
50″C前後の温度で空気雰囲気中にて焼成した後に、
有機系絶縁層11を印刷抵抗体1の上に印刷する。After printing and drying ruthenium oxide printed resistor 1,
After firing in an air atmosphere at a temperature of around 50″C,
An organic insulating layer 11 is printed on the printed resistor 1.
そしてその後50〜200℃程度の温度で硬化させ、そ
の後印刷抵抗体1と絶縁層11で電気的に絶縁され、印
刷抵抗体1とクロスオー・バーする有機系印刷抵抗体1
2を印刷し、150〜200°C程度の温度硬化させる
。After that, it is cured at a temperature of about 50 to 200°C, and then the printed resistor 1 and the insulating layer 11 are electrically insulated, and the organic printed resistor 1 crosses over with the printed resistor 1.
2 is printed and cured at a temperature of about 150 to 200°C.
このようにして絶縁層11で電気的に絶縁された重なり
合う印刷抵抗体1.12を形成する。In this way, overlapping printed resistors 1.12 are formed which are electrically insulated by the insulating layer 11.
以上のように本実施例によれば第1の実施例と同様の効
果を奏するとともに、絶縁層を第1の実施例よりも低温
で形成することができる。As described above, according to the present example, the same effects as the first example can be achieved, and the insulating layer can be formed at a lower temperature than the first example.
発明の効果
以上のように本発明によれば、下層抵抗体の一部分を絶
縁層で覆い、その絶縁層上で上層抵抗体を下層抵抗体に
クロスオーバーして形成することにより、実装密度を高
め、抵抗を精度良くトリミングし、かつトリミングの工
数を減らすことができる。Effects of the Invention As described above, according to the present invention, a part of the lower layer resistor is covered with an insulating layer, and the upper layer resistor is formed by crossing over to the lower layer resistor on the insulating layer, thereby increasing the packaging density. , the resistor can be trimmed accurately and the number of trimming steps can be reduced.
第1図は本発明の第1の実施例における混成集積回路装
置の印刷抵抗部分の断面図、第2図は同抵抗体部分の斜
視図、第3図は本発明の第2実施例における混成集積回
路装置の印刷抵抗体部分の断面図、第4図は同抵抗体部
分の斜視図、第5図(a)は従来例における単層混成集
積回路装置の抵抗体部分の断面図、同図(ハ)は同抵抗
体部分の斜視図、第6図は従来例における多層混成集積
回路装置の印刷抵抗体部分の断面図である。
1・・・・・・下層印刷抵抗体(酸化ルテニューム系)
2・・・・・・絶縁層(無機ガラス系)、3・・・・・
・上層印刷抵抗体(酸化ルテニューム系)、4・・・・
・・Ag/Pd等の導体、5・・・・・・ホーロー基板
、6・・・・・・抵抗トリミング溝、11・・・・・・
絶縁層(有機系)、12・・・・・・上層印刷抵抗体(
を機系)。FIG. 1 is a sectional view of a printed resistor portion of a hybrid integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a perspective view of the same resistor portion, and FIG. FIG. 4 is a cross-sectional view of the printed resistor portion of an integrated circuit device, FIG. 4 is a perspective view of the resistor portion, and FIG. 5(a) is a cross-sectional view of the resistor portion of a conventional single-layer hybrid integrated circuit device. (C) is a perspective view of the resistor portion, and FIG. 6 is a sectional view of the printed resistor portion of the conventional multilayer hybrid integrated circuit device. 1... Lower layer printed resistor (ruthenium oxide type)
2... Insulating layer (inorganic glass type), 3...
・Top layer printed resistor (ruthenium oxide type), 4...
...Conductor such as Ag/Pd, 5...Enamel board, 6...Resistance trimming groove, 11...
Insulating layer (organic), 12... Upper layer printed resistor (
machine).
Claims (1)
とする抵抗体と、前記抵抗体の一部分上に形成した無機
ガラスと有機系絶縁物の少なくとも一方からなる絶縁層
と、前記抵抗体上に前記絶縁層を介して形成した酸化ル
テニュームを主成分とする抵抗体又は有機系抵抗体とを
備えることを特徴とする混成集積回路装置。a resistor mainly composed of ruthenium oxide formed on a hollow substrate; an insulating layer made of at least one of inorganic glass and organic insulator formed on a portion of the resistor; and the insulating layer on the resistor. 1. A hybrid integrated circuit device comprising: a resistor whose main component is ruthenium oxide or an organic resistor;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1140469A JPH034585A (en) | 1989-06-01 | 1989-06-01 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1140469A JPH034585A (en) | 1989-06-01 | 1989-06-01 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH034585A true JPH034585A (en) | 1991-01-10 |
Family
ID=15269324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1140469A Pending JPH034585A (en) | 1989-06-01 | 1989-06-01 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH034585A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104364184A (en) * | 2012-05-15 | 2015-02-18 | 科恩起重机有限公司 | Lifting hook and safety latch for lifting hook |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60214583A (en) * | 1984-04-10 | 1985-10-26 | 日本金属株式会社 | hybrid integrated circuit board |
| JPS61181187A (en) * | 1985-02-07 | 1986-08-13 | 株式会社三協精機製作所 | Manufacture of thick film circuit |
| JPS63306690A (en) * | 1987-06-08 | 1988-12-14 | Hitachi Cable Ltd | Hybrid IC wiring circuit using oxide ceramic superconductor |
| JPH01128588A (en) * | 1987-11-13 | 1989-05-22 | Matsushita Electric Ind Co Ltd | Hybrid integrated circuit device |
-
1989
- 1989-06-01 JP JP1140469A patent/JPH034585A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60214583A (en) * | 1984-04-10 | 1985-10-26 | 日本金属株式会社 | hybrid integrated circuit board |
| JPS61181187A (en) * | 1985-02-07 | 1986-08-13 | 株式会社三協精機製作所 | Manufacture of thick film circuit |
| JPS63306690A (en) * | 1987-06-08 | 1988-12-14 | Hitachi Cable Ltd | Hybrid IC wiring circuit using oxide ceramic superconductor |
| JPH01128588A (en) * | 1987-11-13 | 1989-05-22 | Matsushita Electric Ind Co Ltd | Hybrid integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104364184A (en) * | 2012-05-15 | 2015-02-18 | 科恩起重机有限公司 | Lifting hook and safety latch for lifting hook |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0213958B2 (en) | ||
| GB1329052A (en) | Method of manufacturing thick-film hybrid integrated cirucits | |
| JPH034585A (en) | Hybrid integrated circuit device | |
| JPH034584A (en) | Hybrid integrated circuit device | |
| JPS63141388A (en) | Manufacture of thick film circuit board | |
| JPH01290285A (en) | Hybrid integrated circuit | |
| JPH0239116B2 (en) | ||
| JPH01128588A (en) | Hybrid integrated circuit device | |
| JPS6165465A (en) | Manufacture of film resistor in thick film multilayer substrate | |
| JPS63253659A (en) | Thick film hybrid integrated circuit device | |
| JP2517726B2 (en) | Method for manufacturing multilayer wiring board | |
| JPS58204516A (en) | Thick film multilayer circuit board | |
| JPH0219980Y2 (en) | ||
| JPS62213194A (en) | Thick film circuit board and manufacture of the same | |
| JPS63261796A (en) | Manufacturing method of multilayer hybrid IC board | |
| JPS6313397A (en) | Thick film circuit board with built-in capacitor | |
| JPS61208804A (en) | Manufacture of multilayer interconnection substrate | |
| JPS6390113A (en) | Resistance-capacitor composite component | |
| JP2529037Y2 (en) | Composite board structure | |
| JPS5773959A (en) | Manufacture of thick film hybrid integrated circuit board | |
| JPS63141387A (en) | Manufacture of thick film circuit board | |
| JPS6347248B2 (en) | ||
| JPS63102400A (en) | Thick film circuit board | |
| JPS5992599A (en) | Method of producing thick film hybrid integrated circuit | |
| JPS58142599A (en) | Thick film multilayer board |