JPH0345934B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital PLL (Phose Locked Loop) circuit consisting only of digital circuits.

Conventional configuration and its problems Conventionally, the configuration shown in FIG. 1 is known as a digital PLL circuit. This PLL circuit uses a fixed oscillator 1 that generates a basic clock S1 with a frequency that is an integral multiple of the basic frequency _c of the input clock φ _IN .
, a phase comparator 2 which outputs a phase difference signal S2 with a duty ratio corresponding to the phase difference between an input clock φ _IN and an output clock φ _OUT produced as described later, and a phase lead/lead signal S2 that outputs a phase difference signal S2 with a duty ratio corresponding to the phase difference between an input clock φ IN and an output clock φ OUT produced as described later. A counter section 3 for detecting a delay state as described later, and a basic clock S according to the output signal of this counter section 3.
A clock converter 4 converts a signal by manipulating the number of pulses of 1, and a converted clock S5 processed by this clock converter 4 is divided into an output clock φ _OUT.
It is composed of a frequency divider 5 that obtains .

The phase comparator 2 uses an EOR (exclusive OR) circuit as a simple configuration, and converts the EOR signal of the input clock φ _IN and output clock φ _OUT to the phase difference signal S2.
Output as . The relationship among these signals φ _IN , φ _OUT , and S2 is shown in FIG. In the figure, A to C indicate that the phase of the output clock φ _OUT is ahead of the phase of the input clock φ _IN , N to C indicate a synchronous state, and T to C indicate that the phase of the output clock φ _OUT is ahead of the phase of the input clock φ _IN. It shows that the state is further behind.

As is clear from FIG. 2, the phase difference between φ _IN and φ _OUT can be determined from the time difference between the H level section and the L level section in the phase difference signal S2 for one cycle.
The counter section 3 detects this.

The counter section 3 consists of a K-ary up-down counter circuit, which performs an up-count operation with a predetermined clock when the phase difference signal S2 is at the H level, and performs a down-count operation when the phase difference signal S2 is at the L level. When it counts up to K in the up direction, it outputs a carry signal S3, and when it counts up to K in the down direction, it outputs a borrow signal S4. The count value K is set to correspond to a time equal to or more than half a period of the input clock φ _IN .

Therefore, when the phase of the output clock φ _OUT advances the phase of the input clock φ _IN by more than a certain value, the borrow signal S4 turns on, and on the other hand, when it lags behind the phase, the carry signal S3 turns on.

When both carry signal S3 and borrow signal S4 are off (if the phase of φ _OUT is synchronized with φ _IN ),
The clock converter 4 deletes one pulse for every two pulses of the basic clock S1 to obtain a converted clock S5. In other words, in this state, the signal obtained by dividing the basic clock S1 by 1/2 is the changing clock S1.
5, and the signal obtained by dividing the frequency by 1/N by the frequency divider 5 becomes the output clock φ _OUT . As is clear here, the fixed oscillator 1 oscillates at 2×N times the fundamental frequency _c of the input clock φ _IN .

When the carry signal S3 is turned on (when the phase of φ _OUT lags behind φ _IN ), the clock converter 4 does not perform the above-described pulse deletion process and uses the basic clock S1 as the converted clock S5. That is, compared to the synchronized state in which one pulse is deleted for every two pulses of the basic clock S1, one pulse is added to the conversion clock S5 for every two pulses of the basic clock S1. This advances the phase of the output clock φ _OUT to follow φ _IN .

When the borrow signal S4 turns on (the phase of φ _OUT leads that of φ _IN ), the clock converter 4 successively deletes two pulses of the basic clock S1. In other words,
Compared to the synchronization state described above, the basic clock S1
One pulse of the conversion clock S5 is deleted every two pulses of the conversion clock S5. This delays the phase of the output clock φ _OUT to follow the input clock φ _IN .

The reason why the variable clock S5 is divided by 1/N by the frequency divider 5 and the final output clock φ _OUT is obtained is because this PLL is connected to the fundamental frequency _c of the input clock φ _IN .
This is to reduce jitter in the output clock φ _OUT by operating with a clock that is 2×N times as large as φ OUT, and it is generally desirable to set the value of N as large as the circuit system allows.

The conventional digital PLL circuit described above is composed of a combination of many circuits each having different functions, such as a phase comparator 2, a counter section 3, a clock converter 4, and a frequency divider 5, and has the problem of increasing the circuit scale. It was hot. The large scale of the circuit causes various problems, such as an increase in chip size, even if the entire circuit is integrated into an LSI.
This is a fundamental flaw.

Another problem is that conventional circuits cannot cope with higher speed input clocks. One of the causes
The first is that a fundamental clock with a high frequency of 2×N times the fundamental frequency of the input clock is required. It also includes many circuits with deep logic counter configurations, such as the counter section 3 and frequency divider 5.
This point is also a factor that hinders speeding up.

OBJECTS OF THE INVENTION An object of the present invention is to provide a digital PLL circuit which has a simple circuit configuration and can easily cope with higher speed input clocks.

Structure of the Invention In order to achieve the above object, the present invention divides the frequency of a basic clock using a ring counter with a simple structure using a shift register to obtain an output clock, and adds a simple logic circuit to this to obtain a ring counter. The configuration is such that the number of stages can be increased or decreased, thereby changing the phase of the output clock. In addition, a circuit for detecting the change point of the input clock is provided, and a phase difference detection circuit is provided for detecting the lead/lag between the phase of the input clock and the operating phase of the ring counter based on the output of the circuit and the output of the ring counter. The circuit is configured to increase or decrease the number of stages of the ring counter according to the output of the phase detection circuit.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows a digital system according to an embodiment of the present invention.
This shows the configuration of the PLL circuit. In order to simplify the explanation, this embodiment is configured to operate at a speed six times the fundamental frequency of the input clock φ _IN .

In FIG. 3, a fixed oscillator 6 outputs a fundamental clock S6 having a frequency six times the fundamental frequency of the input clock φ _IN , which is a data string or the like. This one
The PLL circuit operates in synchronization with the basic clock S6.

The input clock φ _IN is applied to the change point detection circuit 7. In response to both the rising and falling changing points of the input clock φ _IN , the changing point detection circuit 7 outputs an edge signal S7. This edge signal S7 is a pulse signal having a width equal to the period of the basic clock S6.

D-type flip-flops F1 to F7 constitute a ring counter 20 using a shift register.
However, two switches 9 and 10, which are part of the stage number control circuit, and an OR gate G5 are combined in the signal path as the ring counter 20.
The number of counter stages can be changed to 5, 6, or 7 stages.

The ring counter 20 operates in response to the basic clock S6, and only one of the flip-flops F1 to F7 is set, and its "1" bit circulates throughout the ring. Therefore, the basic clock S6 is frequency-divided by the ring counter 20, and the output Q of the third stage flip-flop F3 is
The output clock φ _OUT is taken from.

The switching devices 9 and 10 have exactly the same configuration, and are a type of decoder in which outputs A and B are controlled by inputs I and S. FIG. 4 shows the logical relationship between inputs and outputs I, S, A, and B. In other words, when S = “0”, input I is derived to output B, and S
="1", input I is derived to output A.

Therefore, if "1" is applied to the inputs S of both switches 9 and 10, the seven flip-flops F1
~F7 are all connected in a ring, and ring counter 2
0 becomes 7 stages. Further, when the input S of the switch 9 is set to "1" and the input S of the switch 10 is set to "0", six flip-flops F1 to F6 are connected in a ring, and the ring counter 20 has six stages. Further, when the input S of the switch 9 is also set to "0", the five flip-flops F1 to F5 are connected in a ring, and the ring counter 20 has five stages.

The outputs O1 and O2 of the switching control circuit 8 are applied to the inputs S of the switching devices 9 and 10, respectively. Inputs I1 and I2 of this switching control circuit 8 are supplied with the output of a phase difference detection circuit 21 composed of OR gates G1 and G2 and AND gates G3 and G4. The switching control circuit 8 has inputs I1, I2 and an output O.
It is a simple sequential circuit in which the outputs O1 and O2 are controlled by the states of O1 and O2, and the input-output relationship is expressed as
As shown in the figure.

The phase difference detection circuit 21 includes the above-mentioned change point detection circuit 7.
output S7 of the ring counter 20, 1, 2,
4th and 5th stage flip-flops F1, F2, F
The phase of the input clock φ _IN and the lead/lag of the operating phase of the ring counter 20 are detected based on the outputs Q of the input clocks 4 and F5.

When the output S7 of the change point detection circuit 7 becomes "1" (when the edge signal S7 is output),
It is assumed that when the output Q of the fourth stage flip-flop F3 from which the output clock φ _OUT is taken out is “1”, the phases of the input clock φ _IN and the output clock φ _OUT are synchronized. In this state, S7=
When it becomes “1”, flip-flop F1, F
Since the outputs Q of 2, F4, and F5 are all "0", the outputs of OR gates G1 and G2 are also "0",
The outputs of AND gates G3 and G4 (ie, inputs I1 and I2 of switching control circuit 8) are both "0".

When the inputs I1 and I2 of the switching control circuit 8 are both "0", the states of the outputs O1 and O2 do not change, so the number of stages of the ring counter 20 does not change and maintains the current number of stages. Now φ _IN and φ _OUT
will remain synchronized.

Also, when the edge signal S7 becomes "1",
When the output Q of the flip-flop F1 or F2 is "1", it is determined that the operating phase of the ring counter 20 (the phase of the output clock φ _OUT ) lags the phase of the input clock φ _IN . In other words, in this case, when S7="1", the output of OR gate G2 is "1", and therefore
The output (input I2) of AND gate G4 becomes "1".

When the input I2 of the switching control circuit 8 becomes "1", as shown in FIG. 5, the outputs O1 and O2 change to 1,0 if they are 1,1, or change to 0,0 if they are 1,0. . This change in the outputs O1 and O2 is a change that reduces the number of stages of the ring counter 20. That is, if the number of stages of the ring counter 20 is 7 stages, it is reduced to 6 stages, and if it is 6 stages, it is reduced to 5 stages. As a result, the circulation period of the ring counter 20 becomes shorter,
The phase of the delayed output clock φ _OUT is advanced,
It follows the input clock _φIN .

Also, when the edge signal S7 becomes "1",
When the output Q of flip-flop F4 or F5 is "1", it is determined that the phase of the output clock φ _OUT is ahead of the input clock φ _IN ,
The output (input I ₁ ) of AND gate G3 becomes "1".

When the input _I1 of the switching control circuit 21 becomes "1", as shown in FIG. 5, the outputs O1 and O2 change to 1,0 if they are 0. do. This change in the outputs 01 and 02 is a change that increases the number of stages of the ring counter 20. In other words, 5 stages increases to 6 stages, and 6 stages increases to 7 stages. As a result, the circulation period of the ring counter 20 becomes longer, and the phase of the output clock _{φ_OUT} , which had been leading, is delayed, so that it follows the input clock _{φ_IN} .

By the above operation, an output clock φ _OUT whose phase is synchronized with the input clock φ _IN is obtained.

Effects of the Invention As explained in detail above, the digital PLL circuit according to the present invention uses a simple ring counter using a shift register and a simple logic circuit combined with this to perform basic clock frequency division processing and output clock processing. Since all of the phase manipulation processing of the input clock and the phase comparison processing of the input clock and output clock are performed, the overall circuit configuration becomes much simpler and smaller than the conventional one. Furthermore, since the output clock is obtained by directly frequency-dividing the basic clock by 1/N using a ring counter, it is relatively easy to respond to an increase in the speed of the input clock. Further, in the present invention, the number of circuits having a counter configuration with deep logic, which hinders high-speed operation, is greatly reduced.

Furthermore, since the number of stages of the ring counter can be increased or decreased using a simple circuit, the PLL operation can be easily set according to the characteristics of the input clock.

Furthermore, since the amount of positional deviation is detected depending on which flip-flop outputs the signal indicating the position of a specific signal bit, accurate and efficient phase manipulation processing can be realized with a simple circuit. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional digital PLL circuit, FIG. 2 is a timing diagram for explaining the circuit operation of FIG. 1, and FIG. 3 is a block diagram of a digital PLL circuit according to an embodiment of the present invention. 4 is a diagram showing the input/output logical relationship of the switching devices 9 and 10 in FIG. 3, and FIG. 5 is a diagram showing the input/output logical relationship of the switching control circuit 8 in FIG. 3. 6... Fixed oscillator, 7... Change point detection circuit, 8
...Switching control circuit, 9, 10...Switching device, 20...
...Ring counter, F1-F7...Flip-flop, 21...Phase comparison circuit, G1, G2...
OR gate, G3, G4...AND gate, G5...
...OR gate.

Claims (1)

[Claims] 1. A change point detection circuit that detects a change point of an input clock and outputs the detection result, a fixed oscillator that generates a fundamental clock having a frequency that is an integral multiple of the fundamental frequency of the input clock, and a flip-flop are connected in multiple stages, A ring counter which sequentially circulates specific signal bits through the flip-flops in synchronization with the basic clock and extracts an output clock from a flip-flop at a predetermined stage; a phase comparison circuit that detects the lead/lag between the phase of the input clock and the operating phase of the ring counter based on the output; and a flip-flop that operates according to the output of the phase comparison circuit to circulate the specific signal bit. and a stage number control circuit that increases or decreases the number of constituent stages, and the ring counter includes a first switch and a second switch that control the shift of the specific signal bit, and is located upstream of the flip-flop of the predetermined stage. position information indicating the position of the specific signal bit is output from a flip-flop located downstream and upstream of the first and second switching devices to the phase comparator circuit, and the phase comparator circuit When the output is from the flip-flop located upstream, it is determined that the operating phase of the ring counter lags the phase of the input clock;
When the position information is output from a flip-flop located downstream and upstream of the first and second switching devices, it is determined that the operating phase of the ring counter is ahead of the phase of the input clock;
When the position information is not output, it is determined that the operating phase of the ring counter and the phase of the input clock are synchronized, and a detection result is output to the stage number control circuit. A digital PLL circuit characterized in that the number of stages of a flip-flop is controlled by controlling the first and second second switchers.