JPH0345948B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field of the Invention) The present invention relates to a decoding circuit, particularly an AMi (alternate
The present invention relates to a decoding circuit that decodes, using a simple circuit, a pseudo signal that is sent out when a predetermined number of consecutive pulse signals "0" occur when receiving an encoded pulse signal (mark inversion).

(Technical background and problems) AMi code (bipolar code), i.e. signal “1”
In a coding system that inverts the polarity of the signal to positive or negative each time it is input and sends it, if the signal "0" is input consecutively for a predetermined number or more, the clock for receiving the signal is extracted. is no longer carried out. Therefore, on the transmitting side, when a predetermined number or more of signals "0" are continuously input, pseudo signals such as B8ZS and B6ZS are sent out.

Conventionally, when receiving an AMi signal including the pseudo signal, dedicated storage circuits are provided to store the positive side signal component and the negative side signal component of the AMi code, respectively, as will be described later, and the stored contents are stored separately. A pattern peculiar to a pseudo signal and a so-called violation indicating that the signal is a pseudo signal are determined by the above method, and the pseudo signal is forcibly converted to "0" or the like during decoding. However, this decoding circuit has a problem in that it requires a large number of memory circuits, such as flip-flop circuits.

Furthermore, a circuit is known that is configured to determine the presence of a violation included in a pseudo signal at the time of reception, and to directly determine a pseudo signal pattern from the received AMi code. Since this stores the pseudo signal pattern after being decoded, there is no need for storage circuits on the positive and negative polarity sides as described above, and only one set of storage circuits is required. A violation memory circuit is required to detect and store the error, which poses a problem in that the circuit configuration becomes complicated.

(Object and Structure of the Invention) An object of the present invention is to solve the above-mentioned problems, by focusing on the characteristics of the pseudo signal, for example, the B8ZS pattern (000VB0VB), and by focusing on the characteristics of the pseudo signal, for example, the B8ZS pattern (000VB0VB). By adopting a configuration in which positive and negative polarity are stored separately until a voltage (000V) is detected, pseudo signals are detected with a simple circuit configuration and all pseudo signal patterns are forcibly changed to "0" etc. It is possible to decode it into the form. Therefore, the decoding circuit of the present invention is a decoding circuit that receives and decodes an AMi-encoded signal, and includes a positive side storage circuit that sequentially stores positive side signals of the received signal in time series, and a received signal. a negative side storage circuit that sequentially stores negative side signals in time series; and a signal that sequentially stores a sum signal of output signals sequentially outputted in time series from the positive side storage circuit and the negative side storage circuit in time series. a storage circuit; a violation detection circuit that detects a violation signal from the output signals from the positive side storage circuit and the negative side storage circuit; A pattern for clearing the contents of the positive side storage circuit, the negative side storage circuit, and the signal storage circuit to all zeros when the signals from the storage circuit, the negative side storage circuit, and the signal storage circuit each correspond to a pattern corresponding to a pseudo signal.・It is characterized by being equipped with a violation detection circuit.

(Example of the invention) The present invention will be explained in detail below based on the drawings.

Figure 1 is an explanatory diagram for explaining the AMi code, Figure 2 is an explanatory diagram for explaining the pseudo signal pattern (B8ZS pattern), Figures 3 and 4 are examples of conventional B8ZS pattern decoding circuits, and Figure 5 is for the book. An example of the invention is shown.

In the figure, 1 and 7 are pattern violation detection circuits, 2 is an AND circuit, 3 is a pattern detection circuit, 4 and 6 are violation detection circuits, and 5 is a 5
Represents a bit shift register.

FIG. 1A shows an example of an AMi encoded signal.
The AMi code is also called a bipolar code, and as described above, it is an encoding method in which the polarity of the signal is inverted to positive or negative each time a signal "1" is input.

FIG. 1B shows a so-called PPCM signal obtained by extracting only the positive side signal from the AMi signal shown in FIG. 1A.

FIG. 1C shows an NPCM signal obtained by extracting only the negative side signal from the AMi signal shown in FIG. 1A.

FIG. 2A shows an example of a B8ZS pattern which is a pseudo signal. This is a pseudo signal necessary to cause the receiving side to perform clock extraction when a predetermined number of signals "0" are continuously input during AMi encoding as described above.

In the figure, "V" means a signal with the same polarity as the previous signal (as shown in the figure, if the previous signal is "1", "1" is given as "V",
If the previous signal is “0”, it becomes “0” as “V”
In the figure, "B" means a signal with a polarity opposite to that of the previous signal (as shown and in the figure). That is,
"V" is a signal that violates the AMi encoding rules, and when the "V" signal is detected and a signal of a predetermined pattern is received, it is determined that a pseudo signal has been received. Then, when a series of signals with the B8ZS pattern "000VB0VB" is received, if all the series of signals are forcibly decoded into signals such as "00000000",
The clock is decoded into the correct signal and the clock is extracted by a series of signals.

Figures 2B and 2C are shown in Figure 2A, respectively.
These are the positive and negative side signals of the AMi signal.
Shows PPCM and NPCM.

FIG. 3 shows an example of a conventional decoding circuit in which the received AMi signal is stored separately in FFs (flip-flop circuits) for the positive and negative sides.

In the figure, 1 is a pattern violation detection circuit. In this circuit 1, the received AMi signal is separated into a positive polarity side signal (PPCM) and a negative polarity side signal (NPCM) from the left end in the figure, and are sequentially shifted to the right in synchronization with a clock signal.
The pattern is each FF1 to FF8 in the figure and
When stored in FF1' to FF8', each FF
Forcibly clear the illustrated B8ZS pattern “000VB0VB” stored in “0000 0000”. This allows correct decoding.

In such a circuit configuration, it is necessary to provide FFs corresponding to the number of bits of the B8ZS pattern on each of the positive and negative sides, which has the problem of increasing the number of memory circuits.

Fig. 4 shows that the received AMi signal is stored in the FF in the form of a signal in which the positive and negative sides are combined together, and a violation signal "V" is generated at the time of reception.
An example of a conventional decoding circuit that detects and stores it in a shift register is shown.

2 in the figure is an AND circuit, in which the pattern detection circuit 3 detects that the B8ZS pattern "00011011" is stored in FF1 to FF8, and the violation signal "V" is detected in the 5-bit shift register 5. When it is detected that the data has been stored in a predetermined position, all of FF1 to FF8 are forcibly cleared.

In such a configuration, when an AMi signal is received, there is a violation circuit that detects the violation signal "V" and a violation circuit that sequentially stores the violation signal "V" and shifts it in synchronization with the clock. Since it requires a shift register, etc., there is a problem that it becomes complicated.

Therefore, the present invention proposes a pseudo signal such as B8ZS.
By focusing on the characteristics of the pattern, we adopted a configuration in which the positive polarity side and the negative polarity side are stored separately for the first half where the violation signal "V" is detected, for example, until the signal "000V" is detected. , decoding is performed using a simple circuit configuration.
This will be explained below.

In Figure 5, the data received from the left end of the diagram
The positive side (PPCM) and negative side (NPCM) signals of the AMi signal are input sequentially, and FF
1 to FF4 and FF1' to FF4', respectively, the PPCM and NPCM signals are sequentially shifted to the right in synchronization with the clock. And in the figure
Signals corresponding to the logical sum of the output signals from FF4 and FF4' are sequentially stored in FF5 to FF8, and shifted to the right in synchronization with the clock.

6 in the figure is a violation detection circuit,
A signal corresponding to the logical sum of the output signals from FF4 and FF4' is stored in FF5, but during this time,
This circuit detects whether the stored signal is a violation "V" or not. As described above, violation "V" is detected when the output signal from FF4 or FF4' includes a signal having the same polarity as the signal detected immediately before. Then, the violation detection circuit 6 detects that the signal corresponding to the violation signal “V” is in the form of “1”.
After being stored in the FF 5, the detection of the violation signal "V" is sent to the pattern violation detection circuit 7 with a delay of, for example, one clock.

In the figure, reference numeral 7 denotes a pattern violation detection circuit, which is input when the violation signal "V" sent out from the violation detection circuit 6 with a delay of one clock is input. In detecting the violation signal "V", the violation detection circuit 6 determines whether the previous signal when "1" was given to FF5 was on the positive side or on the negative side. A violation signal "V" is detected when a signal having the same polarity as the stored polarity arrives.

When the violation signal “V” is input to the pattern violation detection circuit 7 as described above, the signals stored in FF5 to FF8 are the non-polar signal “0001” of the first half of the B8ZS pattern. Equally, violation detection circuit 6
The result of determining whether "1" in "0001" is a violation, and the signals stored in FF1 to FF4 and FF1' to FF4' have the polarity of the latter half of the B8ZS pattern. When equal to “B0VB”, send a clear signal to all FFs and create B8ZS pattern “000VB0VB”
Forcibly convert it to “00000000” and decrypt it.

In the figure, output I or output is AMi signal at the left end.
After being input to the PPCM or NPCM, it is output with a delay of 6 to 8 clocks (6 to 8 bits). FF1 and FF1' in the figure may be provided as needed and are not necessarily required.

In addition, in one embodiment of the present invention shown in FIG. 5, B8ZS
Although the pattern decoding circuit is shown, it is not limited to this; for example, to decode the B6ZS pattern "0VB0VB", other pseudo signals can be similarly decoded by deleting FF7 and FF8 in the figure. It is something.

(Effects of the Invention) As explained above, according to the present invention, the positive polarity and the negative polarity are Since each signal is stored separately, pseudo signals such as B8ZS included in the AMi signal can be decoded with a simple circuit configuration.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram for explaining the AMi code, Figure 2 is an explanatory diagram for explaining the pseudo signal pattern (B8ZS pattern), Figures 3 and 4 are examples of conventional B8ZS pattern decoding circuits, and Figure 5 is for the book. An example of the invention is shown. In the figure, 1 and 7 are pattern violation detection circuits, 2 is an AND circuit, 3 is a pattern detection circuit, 4 and 6 are violation detection circuits, and 5 is a 5
Represents a bit shift register.

Claims (1)

[Claims] 1. A decoding circuit that receives and decodes an AMi-encoded signal, comprising: a positive side storage circuit that sequentially stores positive side signals of the received signal in time series; and a negative side signal of the received signal. a negative side storage circuit that sequentially stores side signals in time series; and a signal storage circuit that sequentially stores a sum signal of output signals sequentially outputted from the positive side storage circuit and the negative side storage circuit in time series. and a violation detection circuit that detects a violation signal from the output signals from the positive side storage circuit and the negative side storage circuit, and the positive side storage circuit based on the output signal from the violation detection circuit. , a pattern biotechnology that clears the contents of the positive side storage circuit, the negative side storage circuit, and the signal storage circuit to all zeros when the signals from the negative side storage circuit and the signal storage circuit respectively correspond to a pattern corresponding to a pseudo signal; A decoding circuit comprising: a ratio detection circuit.