JPH0347512B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an image storage control circuit used in an image processing apparatus.

(Prior Art) Memory circuits typically have three operating modes: read mode, write mode, and read-then-write mode. When using this memory circuit as an image memory, "0" is written to all image memories only when initializing so that images can be superimposed, and when writing actual image data, the read-then-write mode is used. A method of writing the logical sum of write data and read data using .

Conventionally, when writing image data to image memory, it is necessary to write all the data regardless of the content of the data to be written, so even if the image data is based on white (0), it is necessary to write all the image data. It has the disadvantage that it requires time to write, and it takes a long time to write.

For example, when memorizing a character pattern of 32 x 32 dots, simple characters such as "-" and "2" are mostly white, but all 32 x 32 dots are memorized. I needed to remember.

(Object of the Invention) An object of the present invention is to eliminate such drawbacks and reduce the time required to write image data by providing an operation mode that bypasses writing to the image memory when the content of the write data is "0". An object of the present invention is to provide an image storage control circuit that can be shortened.

(Configuration of the Invention) The configuration of the image storage control circuit of the present invention includes a rewritable storage circuit, an address register that temporarily stores an address to the storage circuit, and a lead that temporarily stores output data read from the storage circuit. a data register; a write data register that temporarily stores input data to be written into the memory circuit; and a write data register that outputs the logical sum of the output of the read data register and the output of the write data register when the operation mode is the logical sum mode; an OR circuit that outputs the output of the write data register when the operation mode is not the OR mode; and a zero detection circuit that generates a zero detection signal when a predetermined number of bits in the contents of the write data register are all "0". , if this zero detection signal is not output, write the output of the OR circuit to the memory circuit in response to a memory access request and generate a control signal, and if the zero detection signal is output, generate the control signal. and a timing control circuit that outputs an access end signal without any delay, and when the write data is "0", writing to the memory circuit is bypassed.

(Example) Next, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an image storage control circuit according to an embodiment of the present invention. This embodiment includes a memory circuit 1, an address register 2, a write data register 3, a read data register 4, an OR circuit 5),
It consists of a "0" detection circuit 6 and a timing control circuit 7. 2A to 2J are operation time charts when the write data of this embodiment is not "0", and FIGS. 3A to 3F are operation time charts when the write data is "0". Note that this operation is explained using negative logic.

Next, the operation when the write data is not "0" will be explained with reference to FIG. The operating mode at this time is a write-after-read mode in which the signal from the input terminal 14 is read, and a "0" detectable mode in which the "0" detectable signal from the input terminal 13 is "1". first,
When writing image data to the image storage control circuit, the address from the input terminal 11 (Fig. 2 a) is stored in the address register 2, and the write data from the input terminal 12 (Fig. 2 b) is stored in the write data register. After being set to 3, an access request signal (FIG. 2c) from input terminal 16 is applied. The data set in this write data register 3 is
Since it is not "0", the "0" detection circuit 6 outputs "0".
No detection signal (FIG. 2d) is generated. This access request signal c is a negative logic pulse signal and activates the timing control circuit 7 at its rising edge. Since the "0" detection signal d is not generated, the timing control circuit 7 outputs a memory access signal (FIG. 2e) to the storage circuit 1. At this time, the access mode to the memory circuit 1 is the read mode. Subsequently, a negative logic first gate signal (FIG. 2, f) is generated from the timing control circuit 7, and the previous data of the write address is output as a read signal (FIG. 2, i). This read signal is stored in the read data register 4 at the rise of the first gate signal f, and its contents are sent to the OR circuit 5.

On the other hand, when the externally applied operation mode is the read-then-write mode, the operation mode of the OR circuit 5 is the OR mode. After the first gate signal f rises, the second gate signal g of negative logic
is generated, and the OR circuit 5 outputs data that is the logical sum of the write data stored in the write data register 3 and the previous data of the storage circuit 1 read from the storage circuit 1 and stored in the read data register 4. be done. Following the second gate signal, a write signal (Fig. 2 h) is generated from the timing control circuit 7, and the data (Fig. 2 i) which is the logical sum of the write data and the previous data of the storage circuit 1 is sent to the storage circuit 1. 1 again. When writing to the memory circuit 1 is completed, a negative logic memory access signal (Fig. 2e)
rises, and an access end signal (j in FIG. 2) is output to the outside.

Next, the operation when the write data is "0" will be explained using FIGS. 1 and 3. The operating mode at this time is read-then-write mode,
"0" is the detectable mode. Further, before the access request signal (FIG. 3c) is applied, the write address (FIG. 3a) is set in the address register 2, and the write data (FIG. 3b) is set in the write data register 3. This write data register 3
Since the content of is "0", the "0" detection circuit 5 outputs a "0" detection signal (FIG. 3d), and this "0" detection signal is connected to the timing control circuit 7. When a negative logic access request signal (FIG. 3c) is applied from the outside (input terminal 16), the timing control circuit 7 is activated at the rising edge of the signal, but by the time this access request signal rises, "0" has already been detected. Since the signal (Fig. 3 d) is generated and the operation mode of the timing control circuit 7 is changed,
Memory access signal to memory circuit 1 (Fig. 3e),
The first gate signal, second gate signal, and write signal are not generated, and the write end signal (third
Figure f) is output to the outside.

As an example of this embodiment, when storing a character pattern of 32 x 32 dots, the input data is 8
The data is temporarily stored in the write data register 3 bit by bit or every 16 bits. In the case of a simple character in which all 8 bits or 16 bits input to this register are "0", by bypassing this white information without storing it in the memory circuit, the memory circuit can be used effectively. Moreover, writing time can also be shortened.

(Effects of the Invention) As explained above, in the present invention, a means for detecting that write data is "0" is provided, and when the write data is "0" when the operation mode is the write-after-read mode. By bypassing writing to the image memory, it is possible to shorten the writing time to the image memory. especially,
If the image data to be written is based on white, the effect is great because most of the data does not need to be written.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIGS. 2 a to j are operation time charts when the write data in FIG. 1 is not "0", and FIGS. This is an operation time chart when the write data in the figure is "0". In the figure, 1...Storage circuit, 2...Address register, 3...Write data register, 4...
Read data register, 5...OR circuit, 6...
..."0" detection circuit, 7...timing control circuit,
11 to 16...signal input terminals, 18, 19...output terminals.

Claims (1)

[Claims] 1. A rewritable memory circuit, an address register that temporarily stores an address to this memory circuit,
a read data register that temporarily stores output data read from the storage circuit; a write data register that temporarily stores image input data to be written to the storage circuit; and an output of the read data register when the operation mode is the OR mode. an OR circuit that outputs the logical sum with the output of the write data register and outputs the output of the write data register when the operation mode is not the logical sum mode; a zero detection circuit that generates a zero detection signal when the zero detection signal is 0'', and a zero detection circuit that generates a control signal that writes the output of the OR circuit to the storage circuit in response to a memory access request when the zero detection signal is not output; and a timing control circuit that outputs an access end signal without generating the control signal when the detection signal is output, and bypasses writing to the storage circuit when the write data is "0". Characteristic image storage control circuit.