JPH0348698B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a PLL circuit that can change the lock range according to the level of an input signal, and is particularly applicable to a stereo multiplex circuit of an FM stereo receiver. The present invention relates to a PLL circuit suitable for use.

(b) Prior art On page 360 of "'85 Sanyo Semiconductor Handbook Monolithic Bipolar Integrated Circuit Edition" published on March 20, 1985, there is a description of an IC (integrated circuit) equipped with a PLL circuit as shown in Figure 2. ) LA3350 is listed. In Figure 2, the voltage applied to input terminal 1 is
The phase of the 19KHz stereo pilot signal is compared with the output signal of the frequency divider circuit 3 in the phase comparator circuit 2. The DC signal corresponding to the phase difference generated at the output end of the phase comparator circuit 2 is amplified by the DC amplifier circuit 4 and then applied to the VCO 5.
The output signal of 5 and the output signal of frequency divider circuit 3 are as follows.
It is synchronized with the 19KHz stereo pilot signal.

Therefore, the 38KHz signal obtained by dividing the output signal of the VCO 5 can be used as a signal for demodulating the left and right stereo signals L and R, and the 19KHz signal can be used as a signal for stereo display. I can do it.

(c) Problems to be Solved by the Invention However, the PLL circuit as shown in Fig. 2 has the risk of generating large phase jitter, and it is difficult to demodulate the output signal of the PLL circuit having phase jitter in the stereo multiplex circuit. When used for
There was a problem that stereo distortion and stereo separation worsened. That is, in the PLL circuit shown in FIG. 2, when the stereo sum signal (L+R) is applied to the input terminal 1 along with the stereo pilot signal, and the level of the stereo sum signal becomes large, the phase comparator circuit 2 enters an incomplete switching state. , and a differential component occurs. When the differential component is amplified by the DC amplifier circuit 4 and applied to the VCO 5, the VCO 5 is modulated and phase jitter occurs, resulting in the above-mentioned characteristic deterioration. Further, the phase jitter also affects the pilot signal detection circuit of the stereo multiplex circuit, causing a problem of malfunction of stereo display.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes a synchronous detection circuit that synchronously detects an input signal of a phase comparator circuit using an output signal of a frequency dividing circuit, and A control circuit that continuously controls the gain of the DC amplifier circuit according to the output signal level of the detection circuit is provided, and when the PLL circuit is locked and an output signal is generated from the synchronous detection circuit, the level of the output signal is adjusted to the level of the output signal. The present invention is characterized in that the gain of the DC amplifier circuit is varied accordingly.

(E) Effect According to the present invention, when comparing the phases of the input signal and the output signal of the frequency dividing circuit that divides the output signal of the VCO, the phases of the two signals do not match, and the PLL
When the circuit is not locked, the gain of the DC amplifier circuit can be set high to widen the lock range and to sufficiently widen the capture range. Also, the phases of both signals match,
When the PLL circuit is locked, it is possible to reduce the gain of the DC amplifier circuit in accordance with the output signal level of the synchronous detection circuit, narrow the lock range, and improve phase jitter in accordance with the output signal level. Prevents the lock from becoming unlocked.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
6 is an input terminal to which, for example, an FM stereo detection output signal is applied as an input signal; 7 is a VCO having a free-run frequency of 76 KHz; 8 is a frequency dividing circuit that divides the output signal of the VCO 7; 9 is a frequency divider for dividing the output signal of the VCO 7; a phase comparator circuit that compares the phase of the 19KHz stereo pilot signal of the frequency divider circuit 8 with the 19KHz frequency divided signal of the frequency divider circuit 8; 10 is a DC amplification circuit that amplifies the output signal of the phase comparator circuit 9 and applies it to the VCO 7;
11 is a synchronous detection circuit that synchronously detects the stereo pilot signal contained in the input signal using the frequency divided signal of the frequency dividing circuit 8; 12 is a stereo display lamp 13 according to the output signal of the synchronous detection circuit 11;
and 14 is a control circuit that generates a control signal according to the output signal level of the synchronous detection circuit 11 and continuously controls the gain of the DC amplifier circuit 10 using the control signal. be. Phase comparison circuit 9, DC amplifier circuit 10, VCO
7 and the frequency dividing circuit 8 constitute a normal PLL circuit, and PLL control is performed so that the phase of the output signal of the VCO 7 matches the phase of the input signal, but the details thereof will be omitted.

However, if the input signal applied to the input terminal 6 is a monaural signal, the PLL circuit will not lock because there is no 19KHz stereo pilot signal. Further, since the output signal of the synchronous detection circuit 11 is not generated, the stereo display lamp 13 is turned off and the control circuit 14 is not operated.

On the other hand, when the input signal is a stereo signal, the phase of the 19KHz stereo pilot signal in the stereo signal and the output signal of the frequency divider circuit 8 is compared in the phase comparator circuit 9, and PLL control is started. Said
At the start of PLL control, the PLL circuit is not yet locked, so the stereo pilot signal and the output signal of the frequency divider circuit 8 are out of phase, and the output signal of the synchronous detection circuit 11 is not generated.
Therefore, the output signal of the lamp trigger circuit 12 is not generated, the stereo display lamp 13 remains off, and the control circuit 14 does not operate. As a result, the gain of the DC amplifier circuit 10 becomes a relatively high first predetermined value, and the capture range of the PLL circuit can be kept wide. When the PLL control continues and the PLL circuit locks onto the stereo pilot signal in the input signal, the output signal of the frequency divider circuit 8 becomes synchronized with the stereo pilot signal, and the output signal of the synchronous detection circuit 11 is generated. When the output signal is generated, an output signal of the lamp trigger circuit 12 is generated accordingly, and the stereo indicator lamp 13 lights up to indicate that a stereo signal is being received.

The output signal level of the synchronous detection circuit 11 changes depending on the electric field strength of the input signal, and increases when the electric field is strong and decreases when the electric field is weak. Now, when a strong electric field input signal is applied to the input terminal 6 and the output signal level of the synchronous detection circuit 11 increases, the level of the output control signal of the control circuit 14 also increases, and the gain of the DC amplifier circuit 10 increases. The width decreases to a second predetermined value. Furthermore, when a weak electric field input signal is applied, the level of the output control signal of the control circuit 14 does not become very large, and the gain of the DC amplifier circuit 10 does not decrease much and becomes the third predetermined value. Therefore, the gain of the DC amplifier circuit 10 can continuously take any value between the second predetermined value and the third predetermined value depending on the electric field strength of the input signal.

As a result, when the PLL circuit is not locked, the gain of the DC amplifier circuit 10 becomes a relatively high first value, and a wide capture range can be ensured. In addition, when the PLL circuit is locked and the received signal is a strong electric field, the gain of the DC amplifier circuit 10 is sufficiently lowered to a second value to greatly improve the degree of improvement of the phase jitter of the VCO during overmodulation. I can do it. Furthermore, if the received signal is in a weak electric field with the PLL circuit locked, the DC amplifier circuit 10
By setting the gain to a third value between the first and second values, it is possible to improve the phase jitter of the VCO and prevent lock loss.

FIG. 3 shows a specific circuit for controlling the gain of the DC amplifier circuit. When the PLL circuit is not locked, the differentially connected first and second transistors 15 and Since the output signal of the synchronous detection circuit 11 is not applied to the base of the synchronous detection circuit 16 and the control circuit 14 does not generate a control signal, the gain of the DC amplifier circuit 10 becomes the first predetermined value. When the PLL circuit locks and a high level output signal is generated from the synchronous detection circuit 11, the first
Transistor 15 is off, second transistor 16
is turned on, and the collector current of the second transistor 16 flows through the resistor 17. Therefore, the emitter current of the current source transistor 18 of the DC amplifier circuit 10 decreases, the mutual conductance Gm of the DC amplifier circuit 10 decreases, and its gain decreases to a second predetermined value. Further, when the PLL circuit is locked and a small level output signal is generated from the synchronous detection circuit 11, the difference current between the collector currents of the first and second transistors 15 and 16 flows to the resistor 17, and the mutual conductance of the DC amplifier circuit 10 increases. decreases in accordance with the voltage drop across the resistor 17, and its gain becomes a third predetermined value. Therefore, by using the circuit shown in FIG. 3, the gain of the DC amplifier circuit 10 can be continuously changed in accordance with the output current of the control circuit 14 .

(G) Effects of the Invention As described above, according to the present invention, when the PLL circuit is not locked, the gain of the DC amplifier circuit can be maintained high, so a wide capture range can be ensured. Furthermore, when the PLL circuit is locked, the gain of the DC amplifier circuit can be reduced, so that the phase jitter of the VCO can be improved, and characteristics such as stereo distortion and stereo separation can be improved. Furthermore, since the gain of the DC amplifier circuit can be continuously lowered in accordance with the electric field strength of the received signal, it is possible to prevent the PLL circuit from losing lock when the electric field is weak.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional PLL circuit, and FIG.
The figure is a circuit diagram showing a specific example of the circuit shown in FIG. 7...VCO, 8...Frequency divider circuit, 9...Phase comparison circuit,
10... DC amplifier circuit, 11... Synchronous detection circuit, 14
...control circuit.

Claims (1)

[Claims] 1. A phase comparator circuit that compares the phase of the input signal and the output signal of a frequency divider circuit that divides the output signal of the VCO and generates an output signal according to the phase difference, and a phase comparator circuit that amplifies the output signal of the phase comparator circuit. , a DC amplifier circuit that controls the oscillation frequency of the VCO by its output signal, and a synchronous detection circuit that synchronously detects the input signal using the output signal of the frequency dividing circuit; Depending on the level of the output signal, a first control signal, a second control signal,
a control circuit that generates a control signal that continuously changes between the first and second control signals, and the control circuit generates the first control signal when the PLL circuit is in an unlocked state. Then, the gain of the DC amplifier circuit is set to a large first value, the PLL circuit is locked,
When an output signal of a predetermined level or higher is generated from the synchronous detection circuit according to the electric field strength of the input signal, the second
generates a control signal, sets the gain of the DC amplifier circuit to a second value smaller than the first value, locks the PLL circuit, and lowers the gain from the predetermined level according to the electric field strength of the input signal from the synchronous detection circuit. When a small output signal is generated, a control signal having a value between the first and second control signals is generated, and the gain of the DC amplifier circuit is set to the first and second values according to the input signal level. A PLL circuit characterized by being set to a value between.