JPH0351015B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a TLB (Translation Lookaside Buffer) used for high-speed translation of virtual addresses to real addresses in a multiple virtual memory system.
This invention relates to a TLB control method for making the TLB function efficiently, particularly when address translation for the same content is performed in different virtual spaces, such as in a common area in multiple virtual spaces.

[Conventional technology]

In a segmentation and paging-based multiple virtual storage system, a virtual space is created for each program (job) to be executed, and each created virtual space has a unique space identification number.
By attaching a segment table specified by the STO and a page table referenced by the segment table, mutual area protection and public area management are performed.

One virtual space is made up of, for example, 256 consecutive segments, each segment is made up of 16 consecutive pages, and one page is made up of a consecutive 4 kilobyte area. Each virtual space is identified by a space identification number STO. Each logical address is represented by a segment number, page number, and displacement within the page.

A dynamic address translation (DAT) mechanism is used to translate the logical addresses of programs running in virtual space into real addresses.

FIG. 2 is a conceptual diagram of the dynamic address translation mechanism, in which 31 is a logical address register, 32 is a space identification number STO, 33 is a segment table,
34 is a page table, 35 is a real address register, 36 is a real storage device, and 37 is a TLB.

In operation, the segment table 33 designated by the space identification number STO is referred to based on the segment number in the logical address register 31, and the page table address indicating the starting point of the page table 34 of the segment corresponding to the segment number is determined. Thereby, the page table 34 is further referred to using the page number in the logical address register 31 to obtain the address of the corresponding real page, that is, the address indicating the starting point of the page on the real storage device 36. This real page address and the intra-page displacement in the logical address register 31 are combined to generate a real address in the real address register 35, and the real storage device 36 or a buffer memory (not shown) is accessed.

Here, the combination of the segment number and page number in the logical address register 31 will be called a logical page address. When this logical page address is converted to a real page address using the segment table and page table,
The address pair is registered in the TLB 37.
The TLB 37 is a high-speed buffer memory that holds a certain amount of translation data of recently used logical addresses and enables direct translation. That is, this is an improvement over the dynamic address conversion method using the segment table 33 and page table 34, which requires two memory accesses and takes a long conversion time. Note that a plurality of entries (table rows) making up the TLB are called a way.

To update TLB37 registration, LRU (Least
This is done by evicting conversion data that has not been used recently and then writing new conversion data based on the Recently Used method.

By the way, in multiple virtual spaces, the system area and common area in which control programs and tables are kept resident have the same real address in each space. Therefore, segments corresponding to these system areas and common areas can share the same page table. Similarly, segments in these areas can share conversion data in the TLB 37. These spatially common segments are called common segments.

In order to make the common segment distinguishable, the second
As shown by CS in the segment table 33 in the figure, a CS (common segment) bit is provided for each segment in the segment table of each space.
CS bit is set to “1”.

Regarding the translation of logical addresses within each common segment area, the space identification number STO is ignored,
The logical addresses of each space are treated as if they were logical addresses of a single space and are translated to real addresses using the same segment and page tables.

In this case, the TLB 37 is also provided with a CS bit (see FIG. 2), which indicates whether or not the data is shared as conversion data for the common segment area.

Immediately after IPL, the virtual space is single (STO#0) as shown in Figure 3a, and the CS bits of all segment entries are cleared to "0", but after that, programs that are processed in parallel As the number of common segments increases, it is multiplexed as shown in Figure 3b (STO#0 to #n), and at the same time, the number of common segments is
CS bit is switched to “1”.

However, when the CS bit of the common segment in the segment table of each of these virtual spaces is switched to "1", the CS bit of the conversion data that should originally be included in the common segment area in the TLB37 is "0". state, and until this is rewritten to CS="1", when attempting to convert a logical address included in the common segment area of the added virtual space, TLB37
It is assumed that there is no conversion data within (TLB Miss). Then, new address translation is performed using the segment table 33 and page table 34, and the obtained translated data is registered in the way based on the LRU logic of the TLB 37 with CS="1". Therefore, multiple pieces of conversion data with the same content are registered in the TLB, and in the subsequent address conversion, the conversion data of multiple ways in the TLB is hit, so-called multi-way hit (Multi-way hit).
way hit) occurs.

Using the example shown in FIG. 3, the process by which multi-way hits occur will be illustrated in FIGS. In FIG. 3, it is assumed that the logical address A in each common segment area of each space (space identification numbers #0 to #n) is accessed.

First, the access state of the logical address A in the single space #0 performed immediately after the IPL in Figure 3a, and at this time, the way #0 of the TLB is
Conversion data with CS="0", STO=#0, and logical address=A is registered, but on the other hand, way #1 has CS="0", STO=#0, and another logical address=B. It is assumed that it is registered.

In the multi-space state of Fig. 3b,
This is a case where access to logical address A is requested from the space of STO #1. However, TLB way #0 has a mismatch with CS=“0” and STO=#0, while way #1 has a mismatch with STO=#0 and logical address=B, resulting in a TLB Miss.

As a result of the TLB Miss in , the conversion data obtained using the segment table and page table of the STO #1 space is registered in the TLB. In this case, CS=1, STO=#1, and logical address=A are registered in way #1 of TLB by LRU logic.

Now, from the STO#0 space to the logical address A
An access request is issued, the conversion data of way #0 matches, and since way #1 has CS=1, the space identification number STO=#1 is ignored,
Here too, an address match is obtained, resulting in a multiway hit.

[Problem that the invention seeks to solve]

The present invention attempts to solve the problem of multiway hits occurring due to redundant translation data being registered in the TLB between common segments in a conventional dynamic address translation mechanism using common segments.

[Means for solving problems]

The present invention transfers new conversion data obtained by converting logical addresses within the common segment area to the TLB.
When registering a way, the space identification number is ignored and the same logical address is checked to see if it exists in the TLB. If so, new conversion data is registered in that way to prevent duplicate conversion. This prevents the occurrence of multiway hits based on data, and its configuration is such that in a multiple virtual memory system equipped with a TLB having common segment bits, the TLB has a common segment bit indicating that it is a logical address of a common segment. When registering a logical address of "1", first check whether the same logical address as the logical address is registered in the TLB, and if it is registered, the common segment bit is set to "1" in that way. ” is registered, and if the logical address is not registered, the logical address whose common segment bit is “1” is registered in the designated way based on LRU logic.

〔Example〕

The details of the present invention will be explained below with reference to Examples.

FIG. 1 is a configuration diagram of a system according to an embodiment of the present invention, in which 1 is a TLB way 1, 2 is a TLB way 23
is a logical address register, 4 is a real page address register, 5 is a space identification number register, 6 is a common segment bit register, 7 to 10 are comparators, 12, 13, 21 and 24 are OR gates,
14, 15, 20, 22, 23, 26 and 27
is a NAND gate, 17 to 19 and 25 are inverters, and 11 is a data selector.

TLB1 and TLB2 are part of the page number and consist of an address (consisting of the part of the page number other than the part that addresses the TLB and a segment number), real page address, space identification number STO, common segment bit CS, and valid bit V. has been done.

In normal TLB reference operation, SET NEW
The ENTRY signal is "0" and the SET NEW ENTRY signal is set to "1" when converting data is registered.

The TLB reference operation in this embodiment is the same as the conventional method. First, when the logical address of the program is set in the logical address register 3, part of the page number in the logical address register 3 is
Given to TLB1 and TLB2. Conversion data of an entry corresponding to a part of the page number is read from TLB1 and TLB2. In the case of way 1, the comparator 7 compares the registered logical address in the read conversion data with the corresponding part in the physical address register 3, and when they match, sets "1" to the AND gate 14. Output.

The comparator 8 compares the space identification number STO in the conversion data read from the TLB 1 and the current space identification number set in the space identification number register 5.
It compares it with STO, and if they match, it outputs "1" to the AND gate 14 via the OR gate 12. The other input of OR gate 12 has the common segment bit in the conversion data read from TLB1.
When CS is given and CS="1", OR gate 1
2 is AND regardless of the value of the output of comparator 8.
“1” is output to the gate 14. That is, CS=
In the case of "1", the comparison result of space identification numbers is ignored.

The other inputs of AND gate 14 also have TLB
The valid bit V in the conversion data read from 1 is given. Therefore, the AND gate 14 determines that the valid bit V="1", that is, TLB
If the conversion data read from 1 is valid and CS="0", comparator 7
HIT when both outputs of and 8 are “1”
1=“1”, indicating that way 1 has been hit.

Similarly, valid bit V in the conversion data read from TLB2 is “1” and CS is “0”.
Then, when the outputs of comparators 9 and 10 are both “1”, HIT2 = “1”, and CS =
If it is "1", HIT2 becomes "1" only when the output of the comparator 9 is "1", indicating that way 2 has been hit.

Furthermore, HIT1 is input to the data selector 11,
By inputting the real page address of HIT2 and way 1, and the real page address of way 2, either HIT1 or HIT2 becomes "1".
When , the real page address of the TLB that was hit appears in the output of the data selector 11.

Next, we will describe the operation of registering new conversion data in the TLB. This registration operation is performed in a manner unique to the present invention when the new conversion data is within the common segment area, that is, when the common segment bit CS="1". In other words, if the same logical address as the conversion data to be registered already exists in the TLB, it will be registered preferentially in that way, and in other cases it will be registered in the way specified by LRU logic. be.

New conversion data to be registered in TLB1 is set in logical address register 3, real page address register 4, space identification number register 5, and common segment bit register 6, respectively.

As in the case of the reference operation, each of TLB1 and TLB2 is given a part of the page number of the logical address register 3, and outputs the conversion data of the corresponding entry. and comparator 7 and comparator 9
compares the registered logical address in the conversion data read from TLB1 and TLB2 with the corresponding portion in the logical address register, and outputs "1" to the inputs of inverters 17 and 18, respectively, when they match.

Here, when the common segment bit of the new conversion data (set in the common segment bit register 6) is "0", "1" is given to one input of the OR gate 21 via the inverter 19, so the AND gate "1" is given to one input of 22.

Furthermore, the LRU DATA signal that is the output of the LRU logic (when this signal is "0", it is registered in way 2, and when it is "1", it is registered in way 1) is given to the other input of the AND gate 22, Moreover,
Since "0" is given from the common segment bit register 6 to one input of the AND gate 23, the LRU DATA signal appears at the inputs of the inverter 25 and the AND gate 26, and in the registration operation.
Since the SET NEW ENTRY signal is “1”,
Write enable when LRU DATA="1"
WE1 becomes “1” and the new conversion data is TLB1
Also, when LRU DATA="0", WE2 becomes "1" and registration is performed in TLB2.

Next, when common segment bit register 6 is set to "1", comparators 7 and 9
The case where either one outputs "1" will be described.

When the output of comparator 7 is “1” (i.e.
If there is old conversion data in TLB1 with the same logical address as the new conversion data), both inputs of the AND gate 23 become “1” and the OR gate 24 outputs “1”. . Therefore, WE1="1", WE2="0", and registration is performed in TLB1 regardless of LRU DATA and regardless of the state of TLB2.

Further, if old conversion data with the same logical address as the new conversion data exists only in TLB2, the comparator 9 outputs "1", and the inverter 18 and AND gate 20
After that, "0" is given to one input of the OR gate 21. The other input of the OR gate 21 is also inputted because the value (“1”) of the common segment bit register 6 becomes “0” through the inverter 19.
The output of 1 becomes "0", and "0" is applied to one input of OR gate 24 via AND gate 22. Also, when the output of the comparator 7 is "0", the other input of the OR gate 24 is connected to the AND gate 23.
Since “0” is given through the OR gate 24
outputs “0”. Therefore, WE1="0",
WE2="1" and regardless of LRU DATA
Registration is performed in TLB2.

Also, although "1" is set in the common segment bit register 6, both comparators 7 and 9 are outputting "0" (that is, an attempt is made to register conversion data in a completely new common segment area). In this case, inverters 17 and 1
8, the inputs of the AND gate 20 both become "1", so the inputs of the AND gate 22 pass through the OR gate 21.
Since "1" is given to one input of the common segment bit register 6 and "0" is given to one input of the OR gate 24 via the AND gate 23, LRU DATA=
When “1”, WE1="1", LRU DATA="0"
When this happens, WE2 becomes "1" and replacement is performed using LRU logic.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to eliminate the possibility of multi-hit when referencing TLB,
If multi-hit occurs, it can be considered as a hardware failure. Furthermore, even when changing the common segment bit in the TLB from "0" to "1", there is no need to issue a purge TLB (PTLB) command, which improves the efficiency of TLB use.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a system according to an embodiment of the present invention.
Figure 2 is an explanatory diagram of a conventional general dynamic address translation mechanism, Figure 3 is an explanatory diagram of multiple virtual spaces and common segment bits (CS bit), and Figure 4 is an explanatory diagram of the multi-hit generation process in TLB. be. In the figure, 1 and 2 are TLB, 3 is a logical address register, 4 is a real page address register, 5 is a space identification number (STO) register, 6 is a common segment (CS) bit register, 7 to 10 are comparators, and 12 , 13, 21 and 24 are OR gates,
14, 15, 20, 22, 23, 26 and 27
is an AND gate, 17 to 19 and 25 are inverters, and 11 is a data selector.

Claims (1)

[Claims] 1 In a multiple virtual memory system equipped with a TLB with common segment bits, the above
When registering a logical address whose common segment bit is "1", which indicates that it is a common segment logical address, in the TLB, first check whether the same logical address as the logical address in question is registered in the TLB, and then register it. If the logical address with the common segment bit set to “1” is registered in that way, and if it is not registered, the logical address with the common segment bit set to “1” is registered in the specified way based on LRU logic. A TLB control method in a multiple virtual memory system characterized by registering logical addresses.