JPH0351331B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization pulse generation circuit that generates one shot pulses synchronized with the leading edge and trailing edge of an input signal.

BACKGROUND ART Conventionally, when configuring various digital systems, it has been necessary to generate one-shot pulses synchronized with the leading edge and trailing edge of an input signal, for example, for the purpose of generating a rotation detection signal of a rotating body. Sex often occurs.

Japanese Patent Publication No. 57-37252 (hereinafter abbreviated as Document 1) shows an example in which a pulse signal synchronized with the edges of an input signal is constructed using three NAND gates, and Fig. A logical configuration diagram thereof is shown, and a signal waveform diagram of each part is shown in FIG. Figure 4A
shows the signal waveform supplied to the input terminal 1, FIG. 4B shows the output signal waveform of the NAND gate 2, that is, the signal waveform appearing at the output terminal 3, and FIG. NAND gate 4
Figure 4D shows the output signal waveform of
It shows the output signal waveform of the NAND gate 5.

Problems to be Solved by the Invention As is clear from FIG.
An output signal with a pulse width corresponding to the delay time of the gate is obtained, but if the block receiving this output signal is far from the circuit block shown in Figure 3, the width may vary due to stray capacitance of the wiring. There is a risk that it will disappear if the pulse is narrow.

Furthermore, when chattering occurs near the edges of the input signal in FIG. 4A, the output signal is affected, causing many problems.

Furthermore, in order to be able to arbitrarily set the pulse width of the output signal, a counter circuit would be combined with the circuit shown in Figure 3. In that case, two sets of the same circuit would be prepared, and one input signal If you try to generate a one-shot pulse that is synchronized with the leading edge and trailing edge of the input signal by synchronizing one with the leading edge and the other with the trailing edge of the input signal, the circuit configuration will become complicated. There was a problem.

Means for Solving the Problems In order to solve the above-mentioned problems, the synchronous pulse generation circuit of the present invention includes a first bistable circuit set at the leading edge of the input signal, and a first bistable circuit connected to the first input terminal. a first coincidence gate, which is supplied with an inverted signal of the input signal and whose second input terminal is supplied with the output of the first bistable circuit; and a first coincidence gate, which is set by the output of the first coincidence gate. a third bistable circuit that is set at the trailing edge of the input signal; a first input terminal of which the input signal is supplied; a second coincidence gate supplied with the output of the circuit, a fourth bistable circuit set by the output of said second coincidence gate, a counter for counting clock signals, and said second bistable circuit. a first control means for causing the counter to perform a counting operation when the circuit or the fourth bistable circuit is set; and a first control means for causing the counter to perform a counting operation when the fourth bistable circuit is set; , a second control means for resetting the third and fourth bistable circuits, and synchronizing the second bistable circuit and the fourth bistable circuit with the leading edge and trailing edge of the input signal. This is characterized by extracting the output signal.

Effects According to the present invention, the pulse width of the output signal can be arbitrarily set according to the frequency of the clock signal, and an output signal synchronized with the leading edge and trailing edge of the input signal can be created by the above-described configuration. .

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a logical configuration diagram of a synchronization pulse generation circuit in an embodiment of the present invention, where 1 is an input terminal to which an input signal is supplied, and 3 is an output terminal from which a synchronization pulse is output. , 6 is a clock terminal to which a clock signal for determining the pulse width of the output signal is supplied.

The synchronous pulse generation circuit shown in FIG. 1 can be roughly divided into an AND gate 24 that counts clock pulses to set the output pulse width;
A counting means consisting of a NAND gate 26 and a counter 50, an inverter 12, bistable circuits 10, 20 and
first gate means consisting of a NAND gate 14;
bistable circuits 30, 40 that operate the counting means in synchronization with the trailing edge of the input signal;
and a second gate means consisting of a NAND gate 21.

To summarize the operation, when the leading edge of the input signal arrives, the first
The gate means activates the counting means and causes the output signal to go to "1". The counting means stops the operation of the first gate means after a predetermined time has elapsed.

Further, when a trailing edge of the input signal arrives, the second gate means responds to the arrival of a trailing edge of the input signal.
The counting means is activated and the output signal is shifted to "1". The counting means stops the operation of the second gate means after a predetermined period of time has elapsed.

A detailed explanation of the synchronization pulse generation circuit shown in FIG. 1 will be given below.

In FIG. 1, a first bistable circuit 10 is configured by cross-coupling the input terminal and output terminal of each of NAND gates 7 and 8, and the first bistable circuit 10 has an input terminal. Set at the leading edge of the input signal applied to terminal 1. NAND gate 9 and
One input terminal and output terminal of each of the NAND gates 11 are cross-coupled connected to the second
A bistable circuit 20 is configured, the input signal is supplied to a first input terminal via an inverter 12 and an AND gate 13, and the first input signal is supplied to a second input terminal.
The output of the NAND gate 14, to which the output of the bistable circuit 10 is supplied,
0 is set.

Also, NAND gate 15 and NAND gate 16
A third bistable circuit 30 is configured by cross-coupling one input terminal and output terminal of each of It is set in . NAND gate 17 and
One input terminal and output terminal of each of the NAND gates 18 are connected in a cross-coupling manner to form a fourth gate.
A bistable circuit 40 is configured, and the first input terminal is
The input signal is supplied via the AND gate 19, and the second input terminal of the third bistable circuit 30 is supplied with the input signal.
The fourth bistable circuit 40 is set by the output of the NAND gate 21 to which the output of the NAND gate 21 is supplied.

On the other hand, the T flip-flop 22 and the T flip-flop 23 constitute a 2-bit counter 50, which counts the clock signal supplied to the clock terminal 6. Further, when the second bistable circuit 20 or the fourth bistable circuit 40 is set, the AND gate 2
The output of the AND gate 24 is also supplied to the output terminal 3 via an inverter 25.

Further, the outputs of the T flip-flops 22 and 23 are supplied to the first and second input terminals of the NAND gate 26, and the output of the NAND gate 26 is used as a reset signal to the first bistable circuit 10 and the third input terminal. It is supplied to a bistable circuit 30.

Note that the second input terminal of the AND gate 13 is supplied with the output of the fourth bistable circuit 40, and the second input terminal of the AND gate 19 is supplied with the output of the second bistable circuit 20. Output is supplied. Further, the second and fourth bistable circuits 2
The outputs of 0 and 40 are supplied to the first and second input terminals of the NAND gate 27.
The output of 7 is supplied to the second and fourth bistable circuits 20 and 40 as a reset signal.
The NAND gate 27 is provided for initializing the circuit and does not contribute to normal operation.

The operation of the synchronizing pulse generating circuit configured as described above will be explained with reference to FIGS. 1 and 2. Figure 2 shows the signal waveforms of each part in Figure 1, Figure 2A shows the signal waveforms supplied to the clock terminal 6, and Figure 2B shows the signal waveforms supplied to the input terminal 1. 2C shows the output signal waveform of the AND gate 19, and FIG. 2D shows the output signal waveform of the NAND gate 15. Figure E shows the output signal waveform of the NAND gate 16, and similarly Figure 2 F, G, H, I, J,
K, L, M, and N are NAND gates 21,
17, 18, AND gate 13, and NAND gates 7, 8, 14, 9, and 11 output signal waveforms are shown. Also, O in Figure 2 is an AND gate 24
Figure 2 shows the output signal waveform of P,
Q indicates the output signal waveforms of the T flip-flops 22 and 23, respectively, and R in FIG.
This shows the output signal waveform of the NAND gate 26, and FIG. 2S shows the output signal waveform of the inverter 25.

With the third bistable circuit 30 and the fourth bistable circuit 40 reset in advance, when the leading edge of the input signal arrives at time _t1 in FIG. 2, the output of the NAND gate 11 is Since the level has shifted to "1", the output level of the AND gate 19 has shifted to "1", and then,
The output level of the NAND gate 21 shifts to "0", thereby setting the fourth bistable circuit 40, and the output level of the NAND gate 17 shifts to "1".
The output level of the NAND gate 18 shifts to "0". In addition, at this time, AND gate 1
Since the output level of the first bistable circuit 10 shifts to "0", the output state of the first bistable circuit 10 is also inverted.

When the output level of the NAND gate 18 shifts to “0”, the output level of the AND gate 24 changes to “0”
Then, the reset of the counter 50 is released, so that the counter 50 becomes ready for counting the clock signal.

When the leading edge of the clock signal arrives at time _t2 , the output level of the T flip-flop 22 shifts to "1", but the output levels of the other gates do not change.

With the arrival of the leading edge of the clock signal at time _t3 , the output level of the T flip-flop 23 shifts to "1", and with the arrival of the leading edge of the clock signal at time _t4 , the output level of T flip-flop 23 shifts to "1".
When the output level of the flip-flop 22 shifts to "1", the output level of the NAND gate 26 shifts to "0", and as a result, the third bistable circuit 3
0 is reset, the output level of the NAND gate 15 shifts to "0", and the output level of the NAND gate 16 shifts to "1". By shifting the output level of the NAND gate 15 to "0"
As the output level of the NAND gate 21 shifts to "1", the fourth bistable circuit 40 is reset, and as a result, the output level of the AND gate 24 returns to "1" and the counter 50 is reset.

When the trailing edge of the input signal arrives at time _t5 , since the output level of the NAND gate 18 has shifted to "1" before then, the output level of the AND gate 13 shifts to "1", and then, The output level of the NAND gate 14 shifts to "0", thereby setting the second bistable circuit 20, the output level of the NAND gate 9 shifts to "1", and the output level of the NAND gate 11 shifts to "1". Shifts to “0”. Note that at this time, the output level of the AND gate 19 shifts to "0", so the third
The output state of the bistable circuit 30 is also reversed.

When the output level of the NAND gate 11 shifts to “0”, the output level of the AND gate 24 changes to “0”
Then, the reset of the counter 50 is released again, so that the counter 50 is in a state in which it can count the clock signal.

With the arrival of the leading edge of the clock signal at time _t6 , the output level of the T flip-flop 22 shifts to "1", and with the arrival of the leading edge of the clock signal at time _t7 , the output level of T flip-flop 22 shifts to "1".
When the output level of the flip-flop 23 shifts to "1" and the output level of the T flip-flop 22 shifts to "1" again due to the arrival of the leading edge of the clock signal at time _t8 ,
The output level of the NAND gate 26 shifts to "0" and the first bistable circuit 10 is reset.
The output level of NAND gate 7 becomes “0”,
The output level of the NAND gate 8 shifts to "1". The output level of the NAND gate 7 is “0”
As a result, the output level of the NAND gate 14 shifts to "1" and the second bistable circuit 20 is reset. As a result, the output level of the AND gate 24 returns to "1" and the counter 5
0 is reset.

In this way, the output terminal 3 in FIG. 1 is synchronized with the leading edge and trailing edge of the input signal as shown in FIG. 2 S, and the pulse width is equal to 2 to 3 periods of the clock signal. An output signal is obtained. Further, the pulse width of the output signal can be arbitrarily set by increasing the number of bits of the counter 50 or by changing the frequency of the clock signal.

By the way, the circuit shown in FIG. 1 has a function of absorbing chattering even if the input signal contains chattering. To explain this pattern, suppose, for example, that chattering occurs between time t ₁ and time t ₄ in Figure 2, and the level of the input signal supplied to input terminal 1 temporarily shifts to "0". However, since the output level of the NAND gate 18 has shifted to "0" before that, the output level of the AND gate 13 does not change, and the second The bistable circuit 20 will not be set and the operation will not become abnormal.

The AND gate 13 and AND gate 19 in Fig. 1 are added for the purpose of absorbing input signal chattering, but if there is no risk of chattering occurring in the input signal, from the previous explanation, As can be seen, there is a means for supplying the output of the NAND gate 18 to the input terminal of the AND gate 13, and a means for supplying the output of the NAND gate 11 to the input terminal of the AND gate 1.
None of the means for supplying input terminals 9 are required. Therefore, in that case, AND gate 13 and AND gate 19 are deleted and inverter 1 is replaced.
2 output directly to NAND gate 7 and NAND
In addition to supplying the input signal to the input terminal of the gate 14, the input signal supplied to the input terminal 1 may be supplied to the input terminals of the NAND gate 15 and the NAND gate 21 immediately after.

In the embodiments of the present invention shown in FIG. 1, the circuits are constructed using NAND gates and AND gates, but these may be replaced with other matching gates. For example, in Figure 1
Change all NAND gates to NOR gates,
Even if all AND gates are changed to OR gates, the circuit will operate normally, just by reversing the polarity of the signal waveform shown in Figure 2.

Effects of the Invention As described above, the synchronous pulse generation circuit of the present invention includes a first bistable circuit 10 set at the leading edge of an input signal, an inverter 12 and an AND gate 13 connected to the first input terminal. a first coincidence gate (NAND gate 14), to which an inverted signal of the input signal is supplied and whose second input terminal is supplied with the output of the first bistable circuit; a second bistable circuit 20 that is set by the output of the gate, a third bistable circuit 30 that is set at the trailing edge of the input signal, and a first input terminal of which the input signal is supplied; a second matching gate (NAND gate 21) whose second input terminal is supplied with the output of the third bistable circuit; and a fourth bistable circuit set by the output of the second matching gate. circuit 4
0 and a counter 50 that counts the clock signal.
and a first control means for causing the counter to perform a counting operation when the second bistable circuit or the fourth bistable circuit is set (in the embodiment shown in FIG. The output of the second bistable circuit is supplied to the terminal, and the output of the fourth bistable circuit is supplied to the other input terminal.
A first control means is constructed by supplying the output of the AND gate 24 to the counter as a reset signal. ), and a second circuit that resets the first, second, third, and fourth bistable circuits when the count value of the counter reaches a predetermined value.
control means (in the embodiment shown in FIG. 1, a NAND circuit whose input terminals are supplied with the outputs of flip-flops 22 and 23 constituting the counter 50)
A second control means is constructed by supplying the output of the gate 26 as a reset signal to the first and third bistable circuits. ), and is characterized in that an output signal synchronized with the leading edge and trailing edge of the input signal is taken out from the second bistable circuit and the fourth bistable circuit, and is relatively simple. With a simple circuit configuration, it is possible to obtain an output signal that is synchronized with the leading edge and trailing edge of the input signal and whose pulse width can be arbitrarily set, which is highly effective.

Further, when the second bistable circuit is set, supply of the input signal to the second coincidence gate is blocked, and when the fourth bistable circuit is set, the input signal is blocked from being supplied to the first coincidence gate. a third control means (in FIG. 1, one input terminal is supplied with an inverted signal of the input signal, and the other input terminal is supplied with the output of the fourth bistable circuit); AND gate 13,
A third control means is constituted by an AND gate 19 whose one input terminal is supplied with the input signal and whose other input terminal is supplied with the output of the second bistable circuit. ) By providing
Even if the input signal includes chattering, it can be absorbed, resulting in a great effect.

[Brief explanation of drawings]

FIG. 1 is a logical configuration diagram of a synchronous pulse generation circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of the circuit in FIG. 1, and FIG. 3 is a logical configuration diagram showing a conventional example. 4 are signal waveform diagrams for explaining the operation of the circuit shown in FIG. 3. 1...Input terminal, 3...Output terminal, 6...Clock terminal, 13, 19...AND gate, 14,
21...NAND gate, 10, 20, 30, 4
0... Bistable circuit.

Claims (1)

[Claims] 1. A first bistable circuit that is set at the leading edge of an input signal, a first input terminal of which is supplied with an inverted signal of the input signal, and a second input terminal of which the first bistable circuit is set. a first coincidence gate supplied with the output of the bistable circuit; a second bistable circuit set by the output of said first coincidence gate; and a third bistable circuit set at the input signal and at the trailing edge. a second coincidence gate whose first input terminal is supplied with said input signal and whose second input terminal is supplied with the output of said third bistable circuit; and said second coincidence gate. a fourth bistable circuit that is set by the output of the gate; a counter that counts the clock signal; and a counter that counts the clock signal when the second bistable circuit or the fourth bistable circuit is set. a first control means for causing the operation to be performed; and a control means for controlling the first, second, and
a second control means for resetting the third and fourth bistable circuits, the second bistable circuit and the fourth bistable circuit being synchronized with the leading edge and the trailing edge of the input signal; A synchronous pulse generation circuit characterized by extracting an output signal. 2 The output of the third coincidence gate, whose one input terminal is supplied with the output of the second bistable circuit and whose other input terminal is supplied with the output of the fourth bistable circuit, is supplied to the counter as a reset signal. The output of the fifth coincidence gate, which constitutes the first control means and whose input terminals are supplied with the outputs of a plurality of flip-flops constituting the counter, is used as a reset signal to control the first and third bistables. 2. The synchronizing pulse generating circuit according to claim 1, wherein the second control means is configured by supplying the synchronizing pulse to the circuit. 3 a first bistable circuit that is set at the leading edge of an input signal; a first input terminal is supplied with an inverted signal of the input signal; and a second input terminal is supplied with an output of the first bistable circuit; a first coincidence gate provided, a second bistable circuit set by the output of the first coincidence gate, and a third bistable circuit set at the trailing edge of the input signal; a second coincidence gate, whose first input terminal is supplied with the input signal and whose second input terminal is supplied with the output of the third bistable circuit; and the output of the second coincidence gate. a fourth bistable circuit that is set; a counter that counts clock signals; and a first bistable circuit that causes the counter to perform a counting operation when the second bistable circuit or the fourth bistable circuit is set. and a second control means for resetting the first, second, third and fourth bistable circuits when the count value of the counter reaches a predetermined value.
control means for blocking the supply of an input signal to the second coincidence gate when the second bistable circuit is set, and controlling the input signal to the second coincidence gate when the fourth bistable circuit is set; third control means for inhibiting the supply of an input signal to the coincidence gate of said second bistable circuit and said fourth bistable circuit to synchronize the leading edge and the trailing edge of said input signal; A synchronous pulse generation circuit is characterized in that it extracts an output signal. 4 The output of the third coincidence gate, whose one input terminal is supplied with the output of the second bistable circuit and whose other input terminal is supplied with the output of the fourth bistable circuit, is supplied to the counter as a reset signal. The output of the fifth coincidence gate, which constitutes the first control means and whose input terminals are supplied with the outputs of a plurality of flip-flops constituting the counter, is used as a reset signal to control the first and third bistables. A second control means is configured by supplying the second control means to the circuit, one input terminal being supplied with an inverted signal of the input signal, and the other input terminal being supplied with the output of the fourth bistable circuit. 6 and a seventh coincidence gate, one input terminal of which is supplied with the input signal and the other input terminal of which is supplied with the output of the second bistable circuit. A synchronous pulse generation circuit according to claim 3, characterized in that the synchronization pulse generation circuit is constructed as follows.