JPH0352108B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data flow processing device, and more particularly to an arithmetic control circuit characterized by having functions of counting the number of arriving data, dividing data, and erasing data.

Conventionally, data flow processing devices do not have functions for counting, dividing, or erasing data, and can perform only one type of processing on a series of data sequences, such as a data sequence obtained by raster scanning an image, and cannot detect the end of processing. It was possible.

An object of the present invention is to provide identification numbers to a series of data strings in order to realize processing of data strings in a data flow processing device, and to assign one type of processing to the same identification number. An object of the present invention is to provide an arithmetic control circuit that realizes a function of changing an identification number when the number of data in a data string satisfies a predetermined condition.

The present invention consists of an input latch and an output latch that sample data in synchronization with a pipeline clock, an arithmetic control section that controls counting, shunting, and extinction depending on the number of data arrivals, and a gate array that generates multiplexer switching signals, etc. , a parameter table memory that temporarily stores instruction codes, counters, and sizes.

The present invention is part of a data flow processing device disclosed in Japanese Patent Application No. 169152/1983. This data flow processing device includes a transferable memory for storing data destination addresses, a parameter table memory for storing instructions, a data memory for temporarily storing input data for one side of a binary operation, and a data memory for temporarily storing input data for one side of a binary operation. A queue memory that waits for data from memory, a processor unit that performs binary or unary operations, and a bus interface that controls data input/output between the ring-shaped pipeline bus and external bus that connect these. It is equipped with

The present invention is located at the same location as the parameter table memory, and has functions for counting, diverting, and erasing the number of arrivals of data from the transferable memory.

The configuration of the present invention has been described above, and its details will be explained with reference to embodiments shown in the drawings below.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is an input latch, 2 is a parameter table memory, 3 is a gate array, 4 is an arithmetic control unit, 5 is an output latch, 11 is an input data value, 12
is a pipeline clock, 13 is a read/write switching signal, 14 is a data value, 15 is size B read data, 16 is size C read data, 17 is counter D read data, 18
is read data of counter E, 19 is written data of counter D, 20 is written data of counter E, 21 is read data of status flag F/S, 22 is read data of instruction code A, 2
3 is a signal S indicating the type of data, 24 is a comparison match signal EQH, 25 is a comparison match signal EQL, 30 is a multiplexer input signal CH, 31 is a multiplexer input signal CL, 32 is a multiplexer switching signal MPX1, 33 is a multiplexer switching signal
MPX2 and 34 are multiplexer switching signals MPX
3 and 35 are multiplexer switching signals MPX4, 3
6 is a carry signal CRY, 37 is a copy flag CPF,
38 is the valid flag USE, 39 is the output data identification number LDUT, 40 is the input data identification number IDIN,
41 is an output data value, and 42 is a status flag F/S write signal.

Input latch 1 latches input data value 11 via pipeline clock 12. The input data value 11 is composed of a signal 23 indicating the type of data, an input data identification number 40, a data value 14, and a read/write switching signal 13.

When the read/write switching signal 13 is “0”, the parameter table memory 2 is accessed and read using the input data identification number 40 as an address, and the size B read data 15 and the size C
The read data 16, the read data 17 of the counter D, the read data 18 of the counter E, the read data 21 of the status flag F/S, and the read data 22 of the instruction code A are generated, and in synchronization with the pipeline clock 12, the read data 17 of the counter D is generated. The write data 19 of the counter E and the write data 20 of the counter E are latched. When the read/write switching signal 13 is "1", the input data identification number 40 is accessed as an address, and the data value 14 is written.

Gate array 3 receives signal 2 indicating the type of data.
3, Status flag F/S read data 21,
The read data 22 of the instruction code A and the comparison match signals 24 and 25 are input, and according to the logical conditions shown in FIG. , generates a carry signal 36.

The arithmetic control unit 4 includes an input data identification number 40, a data value 14, size B read data 15, size C read data 16, counter D read data 17, counter E read data 18, multiplexer input signals 30 to 31, and multiplexer switching. Signals 32 to 35 and carry signal 36 are input, and comparison match signals 24 to 25, output data identification number 39, counter D write data 19, and counter E write data 20 are generated.

The output latch 5 latches the copy flag 37, the valid flag 38, the output data identification number 39, and the data value 14 by the pipeline clock 12, and makes the output data value 41.

FIG. 2 shows the assignment of each field in the parameter table memory 2 in FIG. 1. To explain with reference to FIG. It is divided into a field 17, a counter E field 18, and a status flag F/S field 21. When the size B field 15 and the size C field 16 are used in conjunction with the value of the command field 22, that is, the second
There are cases in which the sizes are N1, N2, N6, and N7 in the figure, and cases in which they are used separately and independently, that is, cases in which the sizes are N3, N4, and N5 in FIG. 2.
When the counter D field 17 and the counter E field 18 are used in conjunction according to the value of the command field 22, that is, the counter C in FIG.
1, C2, C6, and C7, and the case where they are used separately and independently, that is, the counter C in FIG.
There are cases of 3, C4, and C5.

The size is set in advance by the number of arrivals in the arrival diversion or arrival replication command, and the counter is cleared to 0 in advance. The counter is incremented by 1 each time one piece of data arrives. If the counter value matches the size, if it is an arrival diversion command, 1 is added to the identification number of the arrived data and the data is diverted, and if it is an arrival copy command, the number is the same as the identification number of the arrived data. The data is copied to both the ID number and the identification number that is incremented by 1, and then sent.

The distribution command divides the arrived data into identification numbers corresponding to the size. For example, when the size is 2, the identification number changes each time data arrives, such as the original identification number, identification number +1, and identification number +2.

The diversion command sends (N4 + 1) of the arrived data to the original (identification number), and the remaining (N5 - N4)
Send ke to (identification number + 1).

The initial branch flow is to flow only the first (N6+1) that arrived to (identification number), and all the rest to (identification number +
1).

For convolution instructions, the initial value of the counter is 0 (even number)
In this case, the identification number of the odd-numbered data remains unchanged, and the identification number of the even-numbered data is incremented and sent out. If the size and counter match, 2 is added to the identification number and sent.

FIG. 3 is a detailed block diagram of the parameter table memory 2 and calculation control section 4 in FIG. 1.

In the figure, 101 is a magnitude comparator, 102 is a magnitude comparator, 103 is a multiplexer, 104 is a multiplexer, 105 is an adder, 106 is an adder,
107 is a multiplexer, 108 is a multiplexer, 109 is a multiplexer, 110 is an adder,
111 is an AND gate, 112 is the output signal of the multiplexer 104, 113 is the sum signal of the adder 106, 114 is a carry signal of the adder 106, 115
is the output signal of the multiplexer 109, 116 is the output signal of the gate 111, 117 is the least significant bit of the counter E output signal 18, and 118 is the magnitude comparator 1.
This is a signal that becomes "1" when the A side input value of 01 is larger than the B side input value. multiplexer 109
The numbers "0" to "5" written in the figure indicate that the multiplexer input switching signal 35 is "0", respectively.
~ This is the input signal selected when “5”, and 1
19 is the output signal of the multiplexer 103, 120
is the output signal of adder 105.

Data values 14 are written into the parameter table memory 2 in advance before the calculation process is started. The read/write switching signal 13 is used as the switching signal at this time, and writing is performed when this value is "1". The input data identification number 40 is used as the address. The capacity of the parameter table memory 2 is given by the product of the number of input data identification numbers 40 and the total bit width of each field of the parameter table memory 2.

The arithmetic control unit 4 processes the read signals 15 to 18 from the parameter table memory 2,
Its main function is to generate an output data identification number 39.

The size comparator 101 is size B read data 1
5 and the read data 17 of the counter D, and if the former is larger, the signal 118 is output.
is set to 1, and when both are equal, comparison match signal 2
Let 4 be "1".

The size comparator 102 is size C read data 1
6 and the read data 18 of the counter E, and when the two are equal, a comparison match signal 25 is generated.
is set to “1”.

The multiplexer 103 selects the signal 30 as an input when the value of the multiplexer switching signal 32 is "0", and selects the data value 14 as the signal 119 when the value is "1".

The multiplexer 104 selects the CL signal 31 as an input when the value of the multiplexer switching signal 32 is "0", and selects the data value 14 as the signal 112 when the value is "1".

Adder 105 reads data 1 from counter D.
7 and signal 119 are added, and the result is signal 120.

Adder 106 reads data 1 from counter E.
8 and signal 112, the sum is set as signal 113, and when there is a carry, signal 114 is set to "1".
Output.

The multiplexer 107 selects the signal 120 as an input when the multiplexer switching signal 34 is "0", and outputs "0" as the signal 19 when it is "1".

The multiplexer 108 selects the signal 113 as an input when the multiplexer switching signal 33 is "0", and outputs "0" as the signal 20 when it is "1".

The multiplexer 109 selects "0" when the multiplexer switching signal 35 is "0" and selects "1".
When it is , select signal 118, when it is “2”, select signal 117, when it is “3”, select “2”, when it is “4”, select “1”, and when it is “5”, select signal 117. In this case, signal 18 is selected and output as signal 115.

Adder 110 adds the values of signal 115 and signal 40 and outputs the result as signal 39.

Signals 19 and 20 are written into parameter table memory 2 in synchronization with pipeline clock 12.

The number of data arrivals is counted by using the adder 110 to add 1 to the output value 18 of the counter E every time data arrives, and writing the result 20 into the counter E.

Data division is performed depending on whether the input data identification number 40 is output as is as the output data identification number 39. This switching is performed by multiplexer 110.

To erase data, set the valid flag USE38 to “1”
This is done depending on whether it is set to 0 or 0.

Next, the operation from the input latch to the output latch will be explained using a simple example. For example, in the case of arrival diversion,
The input latch 1 in FIG. 1 has an instruction and size set in advance, and a flag (F/S) and a counter are cleared to zero. Every time a piece of data arrives, the instruction is decoded, the size and counter are read, and it is checked whether they match. If they do not match, the identification number is output as is, and if they match, it is identified. Add 1 to the number and output. At the same time, the counter is incremented by 1 and rolled back to its original location. These operate within one clock in synchronization with the pipeline clock.

The flag (F/S) is cleared to 0 in the initial state, and in the initial divert instruction (size + 1)
1 is written after the number of data arrives.

FIG. 4 is a diagram showing the input/output logic relationship of the gate array 3 in FIG. 1. Note that blank spaces in the figure are don't care items. Input signals to the gate array 3 include read data 22 of instruction code A, signal 23 indicating data type S, status flag F/S signal 21, comparison match EQH signal 24, comparison match EQL signal 25, and output signals. has a multiplexer input
CH, CL signals 30, 31, multiplexer switching signals MPX1 to MPX432 to 35, carry signal CRY36, status flag F/S write signal 4
2. Copy flag CPF37, valid flag USE3
There are 8.

Each signal takes the value shown by the output value in FIG. 4 when the output condition is satisfied, and outputs "0" when the output condition is not satisfied. As the code of each instruction, the value of instruction code A in FIG. 2 is adopted.

When the copy flag CPE37 is "1", the output data is copied into two in the next pipeline stage, and when it is "0", it is not copied.

When the valid flag USE38 is "0", the data becomes invalid and disappears at the next pipeline stage, and when it is "1", the data does not disappear.

As explained above, the present invention has the feature that the data identification number can be changed.
Since the processing of a series of data strings can be changed partially or regularly, for example, for image data,
It has become possible to perform special processing only on the edge portions, to count the number of processed data, and to detect the end of processing, greatly increasing the flexibility of processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a diagram showing the assignment of each field in the parameter table memory in FIG. 1, FIG. 3 is a detailed block diagram of the parameter table memory and arithmetic control section in FIG. FIG. 2 is a diagram showing the input/output logical relationship of an array. In the figure, 1 is an input latch, 2 is a parameter table memory, 3 is a gate array, 4 is an arithmetic control unit, 5 is an output latch, 11 is an input data value, 12
is the pipeline clock, 14 is the data value, 15
is size B read data, 16 is size C read data, 17 is counter D read data, 18 is counter E read data, 19 is counter D write data, 26 is counter E
write data, 21 is read data of the status flag F/S, 22 is read data of instruction code A, 101 is a magnitude comparator, 102 is a magnitude comparator, 103-104 are multiplexers, 105-
106 is an adder, 107 to 109 are multiplexers, 110 is an adder, and 111 is an AND gate.

Claims (1)

[Claims] 1. In a data flow processing device, an input latch temporarily stores input data from the outside, a parameter table memory stores instruction codes and processing parameters that are read using addresses that are output from the input latch, and A gate array that generates a signal to the parameter table memory and the calculation control unit based on a part of the output of the input latch and an output from the parameter table memory and the calculation control unit that controls counting, dividing, and extinction according to the number of arrivals of data. and the arithmetic control section controlled by the output of the input latch, the output of the parameter table memory, and the output of the gate array, and performs data division, extinction, and counting. .