JPH0352492A - Fault detection system for duplicated equipment - Google Patents

Abstract

PURPOSE:To pin-point location of a fault and to improve the fault detection capability of the duplicated equipment by collating a data passing through a channel of both systems for call by call in a time division exchange having duplicated channels, and changing the channel in the occurrence of an error. CONSTITUTION:Upon the receipt of time slot error information, a channel change processing means 9 receive the information with a time slot number recognition means 5 to recognize a time slot number having an error. When a central control unit 2 confirms the location of a channel through which the time slot having an error passes, that is, a memory address in a time switch in a channel 1, the channel change processing means 9 changes a memory address of a memory such as a channel store memory 1d of the system 1. As a result, when a time slot error detection means 8 does not receive the time slot error information, it is decided that no fault exists in the memory of the time switch of the system 1. Thus, the fault location is confirmed in a time division exchange having channels being duplicated especially in such a way.

Description

[Detailed Description of the Invention] [Summary] Regarding a fault detection method for a duplexed communication path device in a time-division exchange, data passing through both systems of a duplexed time-division communication path is collated, and if there is a discrepancy, the location of the failure is identified. The purpose is to provide a failure detection method that can determine the failure detection method.
In a time division exchange having a communication path device in which communication path holding memories for controlling reading are duplicated, and a central control device for controlling the communication path device, the same time passed through both systems of the duplex communication path. a data collation circuit that collates slot data and outputs error detection information in the case of a discrepancy; an error storage means that receives and stores error detection information from the data collation circuit and outputs it as error occurrence information; time slot number identification means that inputs an internal operating clock having the same speed as the highway passing through the communication path and a frame clock indicating frame identification of the highway, calculates and outputs the time slot number currently passing through the communication path; and a time slot number holding means for receiving error occurrence information from the error storage means and a time slot number from the time slot number identification means, and storing and holding the time slot number at the time when the error occurrence information was received; timeslot matching means for inputting and comparing the error timeslot number held by the holding means and the timeslot number outputted by the timeslot number identifying means, and outputting matching information when the matching results match; time slot error detection means for outputting time slot error information when simultaneously receiving matching information from the slot matching means and error detection information from the data matching circuit; When time slot error information is received from the detection means, a time slot number is received from the time slot number identification means, and a time slot number corresponding to the time slot number is sent to one channel holding memory of the duplexed channel device. The communication path change processing means changes the address of the communication path holding memory, and the time slot error is detected before and after the communication path change processing means changes the address of the communication path holding memory for each system. An error location determining means is provided for receiving and analyzing the time slot error information received from the means and determining the location where the error has occurred.

[Industrial application field]

The present invention relates to a fault detection method for a duplexed channel device in a time division switch.

The method for detecting communication path failure in a time-division switch is as follows:
A method of passing test data with a specific pattern into a communication path and checking the normality of the pattern of output data after passing, or adding a parity bit to data passing through a communication path inside an exchange. However, a commonly used method is to detect failures in the communication path by checking the normality of parity bits after passing through the communication path.

However, in the former method, it is impossible to test all the communication paths, especially all the memory of the time switch, in view of the effect on communication, and therefore the detection ability is low. Furthermore, the method using parity bits requires generation or detection circuits, and has the economic disadvantage that the scale of the communication path increases by the parity bits in addition to the data bits.

In contrast, with devices that have dual communication paths, it is possible to detect failures by comparing the data passing through both systems.
- Reliability (
7). ．． ,D. We apologize for the inconvenience, but there is a drawback in that it is not possible to specify which system 6 or the like the position of the enemy is when writing a blockbuster.

Among the above, there is a need for a fault detection method 2 that can determine the location of a fault, especially in a time-division exchange with duplex communication paths.

[Prior Art] Fig. 4 is an example of a configuration diagram of a conventional system. In the figure, 41 is a communication path device, 42 is a central control unit, and 43 is a system for transmitting data passing through both systems of a duplex communication path. Verify data 8.
Department.

FIG. 4 shows a time-division exchange with duplexed communication paths, where an overnight verification unit 43 compares the 0 and 1 lines of the duplexed communication paths.
Data passing through the system is constantly checked, and if a discrepancy occurs, the central control unit 42 is notified that an error has occurred in the communication path. When the central control unit 42 receives the error occurrence information, it uses means (not shown) to change the communication path for the day and evening that were placed on the time slot where the error occurred, so that the data passes through the error-free communication path. can do.

However, in the above process, even if it is possible to confirm that an error has occurred in the duplexed communication path, there is no way to confirm which of both systems the error has occurred, and maintenance personnel must use some method to trace the error. I have to do this.
There is a problem.

[Problem to be solved by the invention]

As described above, with conventional duplexing equipment, even if it is possible to confirm that an error has occurred in the duplexed communication path, there is no way to confirm in which of both systems the failure has occurred, and maintenance personnel are burdened with identifying the location of the failure. had to be tracked.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fault detection method that can collate data passing through both systems of a duplex time-division communication path and determine the location of the fault if there is a discrepancy.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, i is the communication path device of the time division exchange, 1 a = 1
d is the main structural part of the communication path device 1, la. ib is a communication path for two systems (0 system, 1 system) each including a time switch; lc, id is a communication path holding memory that controls writing/reading of the time switch. Reference numeral 2 denotes a central control unit that controls the communication path device 1, and 3 compares data of the same time slot that has passed through both systems 1a and lb of the duplex communication path, and outputs error detection information in the case of a discrepancy. 4 is an error storage means for receiving error detection information from the data matching circuit 3 and storing error occurrence information and outputting error occurrence information; 5 is a highway passing through the communication path device 1; Time slot number identification means inputting an internal operating clock of the same speed and a frame clock indicating frame identification of the highway, and calculating and outputting the time slot number currently passing through the communication path; 6 is the error storage stage 1000; Time slot/number holding means which receives the error occurrence information from 4 and the time slot number from the time slot number identifying means 5, and stores and holds the time slot number at the time when the error occurrence information is received; 7, the time slot number holding means; 8 is a time slot collation means for inputting and collating the error time slot number held by 6 and the time slot number output from the 1,000-stage time slot number identification stage 5, and outputting matching information when the collation results match; The time slot error detecting means outputs time slot error information when simultaneously receiving the matching information from the time slot matching means 7 and the error detection information from the data matching circuit 3.

Further, reference numeral 9 is provided in the central control device 2, and when receiving time slot error information from the time slot error detection means 8, receives a time slot number from the time slot number identification stage 5, and receives the time slot number from the time slot number identification stage 5. a communication path change processing means for causing a communication path holding memory IC or 1d of one system of the communication path device to change the address of the communication path holding memory corresponding to the time slot number;
is transmitted from the communication path change processing means 9 to the communication path change processing means 9.
error location determining means for receiving and analyzing time slot error information received from the time slot error detecting means 8 before and after changing the address of the communication path holding memory Ic or Id for each side, and determining the location where the error has occurred; It is.

[For production]

In FIG. 1, a duplexed communication path 1 of a communication path device 1 is shown.
Data of the same time slot passes through a and lb at the same time, and the data of both systems are constantly collated in the data collation circuit 3. If a mismatch occurs in the verification results, the data verification circuit 3 outputs error detection information. The error recording means 4 receives and stores the error detection information from the data collation circuit 3, and outputs error occurrence information to the time slot number holding stage 6.

On the other hand, the time slot number identification stage 5 inputs an internal operating clock having the same speed as the highway passing through the communication path device 1 and a frame clock having the same period as the frame synchronization bit of the highway, and inputs an internal operating clock having the same speed as the highway passing through the communication path device 1 and a frame clock having the same cycle as the frame synchronization bit of the highway, and inputs an internal operating clock having the same speed as the highway passing through the communication path device 1 and a frame clock having the same period as the frame synchronization bit of the highway. Calculate and output the time slot number. The time slot number holding stage 6 constantly receives the time slot number, and stores the time slot number received when the error occurrence information from the error storage means 4 is inputted as the number of the time slot in which the error has occurred. It is determined that there is one, and it is held and sent to the time slot matching means 7.

The time slot verification stage 7 receives the number of the time slot currently passing through the communication path from the time slot number identification stage 5, and compares it with the error time slot number sent from the time slot l/number holding stage 6. Verification is being performed. On the highway passing through the communication path, a time slot with the same number arrives every frame, so the time slot matching means 7 receives the time slot number in which the error occurred from the time slot number holding stage 6 and After the frame, the same time slot number is received from the time slot number identification stage 5. At this time,
Since the error time slot number and the verification result match, the time slot verification means 7 sends matching information to the time slot error detection stage 8.

The time slot error detection stage 8 receives error detection information each time the data collation circuit 3 detects an error, but simultaneously receives error detection information when it receives matching information from the time slot verification stage 7. If this happens, it means that the error has occurred again in the same timeslot as the one in which the error occurred last time. In other words, there is a high possibility that a fixed fault exists in one of the communication paths through which the time slot passed, such as a memory fault in a time switch. Therefore, the time slot error detection stage 8 sends time slot error information to the communication path change processing means 9 provided in the central control unit 2.

When the communication path change processing stage 9 receives the time slot error information, it receives the current time slot number from the time slot number identification stage 5 and learns the number of the time slot where the error occurred.

Since the central controller 2 controls the communication path, the position of the communication path through which the time slot in which the error occurred is determined based on the time slot number, that is, within the time switch (not shown) in the communication path 1. You can check the memory address etc. When you check the memory address etc.,
The communication path change processing stage 9 is a communication path holding memory for one system of the duplexed communication path, for example, an I system communication path holding memory 1d.
change the memory address of. As a result, if the time slot error information is no longer received from the time slot error detection stage 8, it means that there is a fault in the memory of the time switch of the (2) system. However, if time slot error information continues to be sent, there is a high possibility that there is a failure in the 0 system communication path, so in this case, further change the memory address of the 0 system communication path holding memory 1C. , as a result, if time slot error information is no longer received, 0
It can be determined that there was a failure in the memory of the system's time switch. If the error does not disappear even after changing the memory address of the communication path holding memory of both systems, there is a strong possibility that a fault exists in the common part.
Since the error does not occur only in the time slot, but rather in multiple time slots, it can be assumed that the common part is blocked.

The error location determining means 10 receives information regarding changing the communication path holding memory, time slot number information, time slot error information, etc. via the communication path change processing means 9.
The above analysis is performed to determine the error location, and output is performed to a main storage device or a display device (not shown).

〔Example〕

FIG. 2 is a circuit diagram of one embodiment of the present invention, and FIG. 3 is a processing explanatory diagram of one embodiment of the present invention.

FIG. 2 shows an embodiment of the circuit diagram of the main part of the present invention,
In the figure, 21 is a channel device, 22 is a central control unit, 23 is a data matching circuit (M0), 24 is a flip-flop circuit (F+) for storing errors, and 25 is a counter (C) for identifying a time slot number. , 26 is a flip-flop circuit for time slot number holding (F o), 27 is a time slot matching circuit (MI), and 28 is a flip-flop circuit for detecting time slot errors (F2).
, GIGI is an AND circuit.

Hereinafter, a state in which an output is sent out will be described as H, and a state in which no output is sent out will be described as L.

When the data matching circuit 23 detects a mismatch between the data of the time slots that passed through the communication paths of both systems, the data matching circuit 23 outputs an error signal, and the AND circuit G outputs an error signal. The signal is input to the C terminal of the flip-flop circuit 26 through the . Note that at this point, the Q. Since the terminal is at H level, the AND circuit G0 is open, and the error signal is sent to the AND circuit G0.
However, when the error signal from the data matching circuit 23 is input to the CK terminal of the flip-flop circuit 24, the Q terminal becomes H, Q. The terminal becomes L, the AND circuit G0 is closed, and the error signal from the second and subsequent data collation circuits 23 is not inputted to the C terminal of the flip-flop circuit 26.

On the other hand, the counter 25 is reset each time the frame clock is input, counts the internal operation clock, calculates the time slot number, and sends the calculation result to Q0 to Q. The signal is then output to the flip-flop circuit 26 and the time slot matching circuit 27. In this state, when the first error signal from the data matching circuit 23 is input to the C terminal of the flip-flop circuit 26, the D0 to D.
Holds the value of . That is, the time aft number at the time when the error signal is output from the data matching circuit 23 is Q0 to Q.
, s terminals and output.

The data matching circuit 23 enters data matching for the next time slot, and if there is no mismatch, outputs L and continues matching. When one frame has passed and the same time slot in which the error previously occurred arrives, the counter 25 changes the number of the time slot from Q0 to Q. The signal is inputted to one input terminal of the time slot matching circuit 27 via the terminal. At this time, the output data from the Q0 to Q1 terminals of the flip-flop circuit 26, that is, the number of the time slot in which an error was found in the previous frame, is input to the other input terminal of the time slot matching circuit 27. Since both inputs fail, the time slot matching circuit 27 outputs an H signal to the AND circuit G+.
Output.

AND circuit G. Q of the flip-flop circuit 24 is applied to the other terminal of the flip-flop circuit 24 when an error is detected first.

is inputted while remaining at H, so when the output of the time slot matching circuit 27 becomes H, H is inputted to the CK terminal of the flip-flop circuit 28.

At this time, the data matching circuit 23 also performs data matching for the same time slot where the error occurred earlier.
When a mismatch is detected again, the output of the data matching circuit 23 becomes H and is input to the D terminal of the flip-flop circuit 28, which is simultaneously input to the CK terminal and sends an H output from the Q terminal to the central control unit 22. do. The intermediate heat control device 22 knows from this that an error has occurred in the same time slot 2, but at the same time it receives the time slot number output from the Q0 to Q1 terminals of the flip-flop circuit 26, so the error tie L slot is The number 1 can be identified.

When the identification is completed, the central controller 22 sends a flip
A reset signal is sent to the R terminals of the tube circuit 26 and the flip-flop circuit 24 to restore the holding state of both circuits.

Following this, the central control unit 22 determines the location of the error, and the process of the central control unit will be explained with reference to FIG. It is an explanatory diagram about processing of a processing part. In the figure, the same as Figure I (゛-
31a to 31d are time (1゛) switches, 32a to 32d are time switches 31; +
- 31d are communication path holding memories, 33a and 33b are spaces (S)''r, switches, 34 is a data collation circuit, 35 is a communication path change processing unit in the central control unit 2, and 36 is a selector. 32c is a communication path holding memory for writing to the time switches 31a and 31e, 32b,
Reference numerals 32d and 32d are communication path holding memories for successive output of the time switches 3lb and 31d, respectively, but the time switch 31a
, 3]. c. communication path holding memory and time switch 3jb.c. The communication path holding memory for writing the 3id is not shown.

Figure 3 (Part 1) t, T. ．． Then, the data A set at a certain time slot of the input highway...
In the channel holding memories 32a and 32c, the memory write addresses of the time switches 34a and 31c are ``p''
is specified and written to the address p (Add p).

Same keyaki+. ．． Address 7l.q (Add
q). If the 0 system is currently used and the 4 and 1 systems are used as backup, each time slot that passes through both systems is switched by the selector 25, and only the time slots that have passed through the 0 system are output. On the other hand, the data read from the time switches 31h and 31d of both systems are collated in the data collation circuit 34,
If a mismatch is detected, the communication path holding memory is changed in the communication path change processing section 35 through the processing described in the operation of FIG.

FIG. 3 (part 2) shows a state in which the communication path change processing unit 35 has changed the communication path holding memory.

That is, in the figure, time slot 1 of data A in the communication path holding memories 32C and 32d of the l system which is the backup system.
・The memory addresses of ``p'' to ``r''q are respectively
'' to "S". After the change, data is further verified in the data verification circuit 34, and the location of the error is determined based on whether the discrepancy has been resolved.If the location of the error is in the communication path, especially in the time switch sequence, the error location is determined as shown in Figure 2. After the central control unit i1j22 resets the fly-knob flop circuit 26 and the fly-knob flop circuit 24, the error occurs in a different time slot, so it is determined that the error is in the space switch or the common part. can. Errors in the common section can also be detected by the fault detection function of the switch, but the above method can be used to detect errors in the space switch or the common section. It is also possible to determine a single location by using a method in which test data having a specific pattern is passed through the communication path after J-Y determination.

In addition, in the above explanation, the communication path structure is changed from a two-stage time switch to a one-stage space switch.
T-3 'T configuration 4}・However, the present invention can also be applied to communication channels with only a time switch and other configurations. :, is obvious. In addition, in the communication path change processing section, the communication path maintenance function 2' of the Y-side system is changed at the same time, but it is easy to change them one by one.
：゛It is possible. Furthermore, ζ, 2. If a discrepancy/coincidence is detected in the same time spot 1- twice in a row in the data matching circuit, the time ``7.Is the lot error information sent to the central control device l times or 3 times? It is also easily possible to transmit time slot error information by detecting discrepancies and coincidences more than once.These are all modifications of the embodiments of the present invention, and the present invention does not exclude these embodiments. .

〔Effect of the invention〕

As explained above, according to the present invention, in a time division exchange having duplex communication paths, data passing through both communication paths is compared call-by-call, and the communication path is changed when an error occurs. This makes it possible to determine the location of a fault, which greatly contributes to improving the fault detection ability of such a duplexing device.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a diagram explaining processing of an embodiment of the invention, and Fig. 4 is a diagram illustrating the configuration of a conventional system. Inside, 1---------1-1--------1 channel device la, lb 1.11111 channel lc
,1d -...1...1 Communication path holding memory 2
・−・・１・− ・１ Central control device 3 ・・・・
1・−−11−−・−・−1−1～・−Data collation circuit 4−・−・1・−・−・・・−−−−11−1 Error storage means 6 Time slot number Hold 9 ・・・〜・−・・−・−−−−−−11・−・1
0 − ・−・・−・1・1・11111111. Means Time Slot Verification Means Time Slot Error Detection Means Communication Path Changing Means Error Location Determination Means 1 Figure 2 Figure 31a Yoya 3lb

Claims (1)

[Claims] A communication path (1a, 1b) including a time switch and a communication path holding memory (1a, 1b) that controls writing/reading of the time switch.
c, 1d) are each duplicated.
) and a central control device (2) that controls the communication path equipment, the data of the same time slot that has passed through both systems of the duplexed communication path is compared, and if there is a mismatch, an error is detected. a data collation circuit (3) that outputs information; an error storage means (4) that receives and stores error detection information from the data collation circuit and outputs it as error occurrence information; and a highway that passes through the communication path device. a time slot number identification means (5) which inputs an internal operating clock having the same speed as that of the highway and a frame clock indicating the frame identification of the highway, calculates and outputs the time slot number currently passing through the communication path; time slot number holding means (6) for receiving error occurrence information from the storage means and time slot number from the time slot number identification means, and storing and holding the time slot number at the time when the error occurrence information is received; time slot matching means (7) for inputting and comparing the error time slot number held by the means and the time slot number output by the time slot number identifying means, and outputting matching information when the matching results match; time slot error detection means (8) for outputting time slot error information when simultaneously receiving coincidence information from the time slot matching means and error detection information from the data matching circuit; ), when the time slot error information is received from the time slot error detection means, the time slot number is received from the time slot number identification means, and the time slot number is stored in the communication path holding memory of one system of the duplex communication path device. On the other hand, the communication path change processing means (9) changes the address of the communication path holding memory for the time slot number; The duplexing apparatus is characterized in that the duplexing apparatus is provided with an error location determining means (10) for receiving and analyzing the time slot error information received from the time slot error detecting means before and after each change, and determining the location where the error has occurred. Fault detection method.