JPH0353338A - Variable priority arbitrating circuit - Google Patents

Abstract

PURPOSE:To apply an arbitrating method suited to each time point by setting a writable priority pattern to a register from a processor to change the priority of arbitration. CONSTITUTION:The (n) pieces of fixed priority arbitrating circuits 13 have different priority patterns, and these priority patterns are selected by the priority pattern selection signals SEL1 - SELn which are outputted from a priority pattern register 11 and a priority pattern selection decoder 12. Thus the circuits 13 arbitrate the priority based on each priority pattern. Then the internal request grant signals ACK1' - ACKm' are outputted to the one having the highest priority out of (m) pieces of request signals REQ1 - REQm. A logical arithmetic means secures the ANDs of the signals ACK1' - ACKm outputted from each means 13 via a AND circuit 14 and outputs the request grant signals ACK1 - ACKm. As a result, the arbitration is attained with use of an optimum priority pattern at each time point.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a data processing device, and in particular, a variable priority arbitration circuit that arbitrates when a large number of requesters request the use of one object at the same time. Regarding.

〔overview〕

The present invention provides a priority arbitration circuit that inputs m request signals, performs arbitration according to the priority order, and outputs m request permission signals, including n fixed priority arbitration circuits each having a different priority pattern. By making it possible to arbitrarily select the fixed priority arbitration circuit according to data input from the outside, a variable priority arbitration circuit is realized that can appropriately change the priority order according to the time. .

[Conventional technology]

Conventionally, this type of priority arbitration circuit includes one that uses a fixed priority method and one that uses a round robin method in which the priority order changes every arbitration cycle.

[Problem that the invention seeks to solve]

Among the conventional priority arbitration circuits mentioned above, those that use a fixed priority method can
If a plurality of requesters with higher priority continue to issue requests alternately, there is a drawback that service may not be available even after a fixed time interval has elapsed. Further, in the method using the round robin method, although the service to each requester is averaged, a particular requester cannot receive the service continuously, so there is a drawback that peak performance is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable priority arbitration circuit that eliminates the above-mentioned drawbacks and allows requests to be granted at least at fixed time intervals even for the lowest priority requester.

[Means for solving problems]

The present invention provides a priority arbitration circuit equipped with an arbitration means for inputting m request signals (m is a natural number), arbitrating according to the priority order, and outputting m request permission signals, wherein the arbitration means is provided with an external signal. n pieces (n
is a natural number), and a priority pattern selection signal generating means, each having a different priority pattern, sequentially outputs the m request signals and the n priority pattern selection signals. n fixed priority arbitration means each inputting one signal at a time, performing arbitration based on the input priority pattern selection signal, and outputting m internal request permission signals; and n fixed priority arbitration means each inputting m internal request permission signals. m logical operation means for inputting the m internal request permission signals corresponding to the same request signal outputted from the apparatus, performing logical operations, and respectively generating and outputting request signals corresponding to the same request signal. do.

[Effect]

The n fixed priority arbitration circuits each have a different priority pattern, are selected by a priority pattern selection signal output from the priority pattern selection signal control means, and perform arbitration based on each priority pattern. and outputs an internal request permission signal to the request signal with the highest priority among the inputted m request signals. Then, the logic operation means uses, for example, an OR circuit to logically OR the internal request permission signals outputted from each fixed priority arbitration means, and outputs the result as a request permission signal.

Therefore, arbitration can be performed using an appropriate priority pattern at that time.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

The figure is a block diagram showing an embodiment of the present invention.

In this embodiment, m (m is a natural number) request signals REQ, ~
REQ. In the priority arbitration circuit, the arbitration means is provided with an arbitration means that receives an input signal, performs arbitration according to the priority order, and outputs m request permission signals ACKI to ACKI. n (n is a natural number) priority pattern selection signals SEL. A priority pattern register 11 and a priority pattern selection decoder 12 as priority pattern selection signal generation means for generating and outputting ~SEL, , and m request signals REQ, -, each having a different priority pattern. REQ, and the n priority pattern selection signals SEL, , S
EL2, , SEL. are input in sequence one by one, and the input priority pattern selection signal SEL. ,SEL2,
, or S E L,, respectively.
n fixed RG priority arbitration circuits 13 that output internal request permission signals ACK,'~ACK', and identical request signals R E Q + output from each of the n fixed priority arbitration circuits 13; R E Q2, or REQ,
m internal request acknowledgment signals ACK. ',A
CK2', or ACK. ' are input and logical operations are performed to obtain the same request signals R E Q + and R E respectively.
Request signal ACK for Q2, or REQII
, ,ACK. , , or ACK. Outputs the living command m
It includes an OR circuit 14 as a logical operation means.

Next, the operation of this embodiment will be explained.

The priority pattern register 11 is a log data that can be written from a processor (not shown) via the data bus a.
This is a 2n-bit wide register, and the value written here selects one of n types of priority patterns.

Output encoded priority pattern data b.

The priority pattern selection decoder 12 receives priority pattern data b from the priority pattern register 11 and outputs n priority pattern selection signals SEL, ~SEL.
, , and output.

The fixed priority arbitration circuit 13 receives m request signals REQ. ~REQ. arbitration is performed in a certain priority order, and the resulting internal request permission signals ACK+' to ACK.
' is output. The arbitration operation is performed using the priority pattern selection signal SE input from the priority pattern selection decoder 12.
LI~SEL. If not selected, the internal request permission signal ACK,'~ACK. ' are all disallowed. The n fixed priority arbitration circuits 13 are
The priority pattern selection signal SEL is input to the l-th stage, and the priority pattern selection signal SE is input to the n-th stage.
L. are input, and each performs an arbitration operation based on a different priority order pattern.

The OR circuit 14 receives internal request permission signals ACK+' to A of the n fixed priority arbitration circuits 13 for the same requester.
C.K. ', and generates and outputs a request permission signal ACK, ACK, which is returned to the requester.

〔Effect of the invention〕

As explained above, according to the present invention, the arbitration priority can be changed by setting the priority pattern register that can be written from the processor, so that an arbitration method suitable at that time can be applied. effective.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the present invention. 11...Priority pattern register, 12...Priority pattern selection decoder, l3...Fixed priority arbitration circuit, 14...OR circuit, ACK, ~ACK.・
...Request permission signal, ACKI '~ACKI,'...
Internal request permission signal, REQ, ~REQ,... request signal, SEL1~SEL,... priority pattern selection signal, a... data path, b... priority pattern data.

Claims (1)

[Scope of Claims] 1. A priority arbitration circuit comprising arbitration means for inputting m request signals (m is a natural number), performing arbitration according to priorities, and outputting m request permission signals, the arbitration means comprising: has priority pattern selection signal generation means for generating and outputting n priority pattern selection signals (n is a natural number) corresponding to data input from the outside, and m priority pattern selection signals, each having a different priority pattern. the request signal and n
m input priority pattern selection signals one by one in sequence, performs arbitration based on the input priority pattern selection signals, and outputs m internal request permission signals, respectively.
and m internal request permission signals for the same request signal outputted from each of the n fixed priority arbitration means, and perform a logical operation to make a request for each of the same request signals. 1. A variable priority arbitration circuit comprising: m logical operation means for generating and outputting signals.