JPH0353339A - Variable priority arbitrating circuit - Google Patents

Abstract

PURPOSE:To enable even a requester of the lowest priority to obtain the grant of requests at a fixed time interval at the lowest by changing the priority at a fixed time interval. CONSTITUTION:The priority change request means 11 and 12 produce the prior ity change request signals a and b at a fixed time interval to the request signals REQ1 - REQn and output continuously the signals a and b until they are granted. A priority deciding means 13 sets the priority as REQ1>REQ2>...>REQn if both signals a and b are not inputted and then decides the priority as REQn> REQ1>...>REQn-1 with input of both signals a and b respectively. Then the means 13 outputs continuously the internal request grant signals ACK1' - ACKn' in accordance with the request time of a continuous request signal BUSY. Then a request grant signal production means 14 samples the signals ACK1' - ACKn' via an arbitration clock signal CLK and produces and outputs the request grant signals ACK1 - ACKn. As a result, even a requester of the lowest priority can obtain the grant of requests at a fixed time interval at the lowest.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a data processing device, and in particular, a variable priority arbitration circuit that arbitrates when a large number of requesters request the use of one object at the same time. Regarding.

〔overview〕

The present invention provides a priority arbitration circuit that manually arbitrates n request signals according to their priorities and outputs n request permission signals. By changing the priority of request signals, a variable priority arbitration circuit is realized in which requests are granted at least at fixed time intervals even for the requester with the lowest priority.

[Conventional technology]

Conventionally, this type of priority arbitration circuit includes one that uses a fixed priority method and one that uses a round robin method in which the priority order changes every arbitration cycle.

[Problem that the invention seeks to solve]

Among the conventional priority arbitration circuits mentioned above, those that use a fixed priority method can
If a plurality of requesters with higher priority continue to issue requests alternately, there is a drawback that service may not be available even after a fixed time interval has elapsed. Further, in the method using the round robin method, although the service to each requester is averaged, a particular requester cannot receive the service continuously, so there is a drawback that peak performance is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable priority arbitration circuit that eliminates the above-mentioned drawbacks and allows requests to be granted at least at fixed time intervals even for the lowest priority requester.

[Means for solving problems]

The present invention provides n request signals REQ, , REQ2, , R
EQ. In the priority arbitration circuit, the arbitration means inputs an arbitration clock signal, performs arbitration according to the priority order, and outputs n request permission signals. a priority change means for generating a priority order change request signal for changing the priority order to the highest priority order and continuously outputting the request signal until the request signal is granted; a previous request permission signal; a continuation request signal requesting continuation of the permission state;
The priority order change request signal is input manually, and if there is no priority order change request, the priority order is REQ + > R E
Q2 >-- > R E Qn, and if there is a priority request, the priority is REQ, >REQ, >--
> R E Qn − + performs arbitration, and as a result, an internal permission signal corresponding to the request signal with the highest priority among the request signals being requested is granted during the period in which the continuation request signal is issued. priority determining means for outputting the state and request permission signal generating means for generating and outputting the n request permission signals by sampling the n internal permission signals outputted from the priority determining means using the arbitration clock signal. It is characterized by including.

[Effect]

The priority change requesting means generates a priority change request signal for changing the priority of the request signal from the lowest priority to the highest priority at fixed time intervals, and continues until the request signal is granted. and output it. The priority determining means determines the priority as REQ+ > REQ2 >> REQl, if there is no human power for the priority change request signal, and determines the priority as REQ, , if the priority change request signal is input. >REQ, >->REQ, , - is determined, and the internal request permission signal is continuously output for the required time of the continuation request signal. Then, the request permission signal generating means samples the internal request permission signal using the arbitration clock signal and generates and outputs a request permission signal.

Therefore, even the requester with the lowest priority will be allowed to make a request at least at certain time intervals.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

The figure is a block diagram showing an embodiment of the present invention.

In this embodiment, n request signals REQ, . -ACK. In the priority arbitration circuit, the arbitration means is characterized in that the arbitration means inputs an arbitration clock signal CLK and selects priority levels from the lowest priority to the highest priority at regular time intervals. A timer 11 and a flip-flop (FF) 12 serve as priority change request means for generating priority change request signals a and b for changing the priority order and outputting them continuously until the request signals are granted.
, n request signals REQ, ~REQ, n request permission signals ACK, ~ACK, , a continuation request signal BUSY requesting continuation of the permission state, and a priority change request signal a. However, if there is no priority change request, the priority is REQ+ >REQ2>->REQ, and if there is a priority request, the priority is REQ.
．． >REQ, >->REQl, -, and as a result, the request signal REQ. -REQ
, , the request signal REQ, ~R with the highest priority
E Q. Internal permission signal ACK, ~ACK corresponding to
An encroachment order judgment circuit 3 as a priority order judgment means which outputs n' in a permission state during the time when the continuation request signal BUSY is issued, and n internal permission signals outputted from this priority order judgment circuit l3. ACK,'~ACKh' as arbitration clock signal CL
n request acknowledgment signals ACK, ~AC sampled by K
K. The arbitration flip-flop 14 includes n flip-flops FF1 to FF, and serves as a request permission signal generating means for generating and outputting a request permission signal.

Next, the operation of this embodiment will be explained.

The timer 11 is for requesting a priority change at regular time intervals, and divides the arbitration clock signal CLK and inputs the result to the clock terminal of the flip-flop 12 as a priority change request signal a.

The flip-flop 12 holds the priority change request signal a from the timer 11 until the requester's request whose priority is changed from the lowest priority to the highest priority is granted. Then, the priority change request signal b sent to the priority determination circuit 13 is maintained in a request state by the priority change request signal a from the timer 11. This state is the request permission signal A.
It is reset when CK is in the permitted state.

The priority determination circuit 13 receives request signals REQ, , REQ2, - , REQ, from n requesters, and a continuation request signal BUSY, which is a busy signal for requesting that the requester whose request has been granted request continuation of the permitted state. and n request permission signals ACK+, ACK2, which convey the arbitration result to each requester.
, ACKh and the priority change request signal a are manually generated, and the internal permission signal ACK. 'ACK2', one, ACK
．． ' is output to the arbitration flip-flop 14. i=1
.about.n, the internal permission signal ACKI' is expressed by the following equation. Note that arbitration is performed using request permission signals ACK,,ACK2
, ,ACK, , are all performed when the permission is not granted.

REQn+b) ・REQ. +ACK+ ・BUSY
The arbitration flip-flop 14 receives n internal permission signals ACK. ' , ACK
2', A C K. ' to arbitrate clock CLK
ACK, a request permission signal for each requester.
,ACK2, ,ACK. Create.

When requester i has a request, requester i sends a request signal REQ. makes a request and waits until the request permission signal A C K l goes into the permission state. When the request permission signal ACKi enters the permission state, the request signal REQI is set to the non-request state, and at the same time, the continuation request signal BUSY is set to the continuation request state for a period during which the permission state is desired to continue.

Requester n usually has the lowest priority, so requester 1-
When there are n-1 requests alternately, the request signal ACK. is in a disallowed state, but if the priority becomes the highest every cycle of the priority change request signal a output from the timer 11 and the request is kept waiting, then the request signal ACK, , becomes a permitted state. .

〔Effect of the invention〕

As described above, the present invention has the effect that by changing the priority order at fixed time intervals, even the lowest priority requester is allowed to make a request at least at fixed time intervals.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. l1...Timer, 12...Flip-flop (F
F), 13...Priority determination circuit, 14...Arbitration flip-flop, a, b...Priority change request signal, ACK. ---Request permission signal, AC
K,'~ΔCK,'...Internal enable signal, BUSY...
・Continuation request signal, CLK...Arbitration clock signal, RE
(L-REQ,...request signal.

Claims (1)

[Claims] 1, n request signals REQ_1, REQ_2, . . .
In a priority arbitration circuit, the arbitration means inputs REQ_n, performs arbitration according to the priority order, and outputs n request permission signals. priority change request means for generating a priority change request signal for changing the priority from the highest priority to the highest priority and continuously outputting the request signal until the request signal is granted; The initial request permission signal, the continuation request signal requesting continuation of the permission state, and the priority change request signal are input, and if there is no priority change request, the priority is REQ_1>REQ_2>...> REQ_n,
If there is a priority request, the priority is REQ_n>R
Arbitrate with EQ_1>...>REQ_n_-_1,
As a result, priority determining means outputs an internal permission signal corresponding to the request signal with the highest priority among the request signals for which a request is made, in a permission state for the time when the continuation request signal is issued; and request permission signal generation means for sampling the n internal permission signals outputted from the priority determination means using the arbitration clock signal and generating and outputting the n request permission signals. arbitration circuit.