JPH0353559A - Integrated circuit package - Google Patents
Integrated circuit packageInfo
- Publication number
- JPH0353559A JPH0353559A JP1189486A JP18948689A JPH0353559A JP H0353559 A JPH0353559 A JP H0353559A JP 1189486 A JP1189486 A JP 1189486A JP 18948689 A JP18948689 A JP 18948689A JP H0353559 A JPH0353559 A JP H0353559A
- Authority
- JP
- Japan
- Prior art keywords
- package
- terminals
- integrated circuit
- semiconductor integrated
- hollow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路パッケージに関し、特に複数の封入済
み半導体集積回路を実装できる集積回路パッケージに関
する.
〔従来の技術〕
従来、封入済み半導体集積回路をプリント配線基板に実
装する場合は、第3図に示すように、2次元的に配置す
る方法、又は、第4図に示すように、・一方向にしか外
部端子23がない封入済み半導体集積回路24を縦に並
べて3次元的に配置する方法が使用されている.
しかし、最近の半導体集積回路の高密度実装化に対する
ユーザの要求に対し、第3図の方法では現状以上の高密
度実装化が困難であり、第4図の方法では、高密度実装
が可能となるが、プリント配線基板上に接続する端子の
単位面積当りの密度が高くなるため、実装が難しくなり
、又、一方向にしか端子がない封入済み半導体集積回路
24は、入出力端子の多い半導体集積回路に対応できな
いという欠点があった。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit package, and more particularly to an integrated circuit package in which a plurality of encapsulated semiconductor integrated circuits can be mounted. [Prior Art] Conventionally, when mounting an encapsulated semiconductor integrated circuit on a printed wiring board, two-dimensional arrangement as shown in FIG. 3 or one-dimensional arrangement as shown in FIG. A method is used in which encapsulated semiconductor integrated circuits 24 having external terminals 23 only in one direction are vertically arranged in a three-dimensional manner. However, in response to recent user demands for high-density packaging of semiconductor integrated circuits, the method shown in Figure 3 makes it difficult to achieve higher-density packaging than the current level, while the method shown in Figure 4 does not allow for higher-density packaging. However, since the density of terminals connected to the printed wiring board per unit area increases, mounting becomes difficult, and the encapsulated semiconductor integrated circuit 24, which has terminals only in one direction, is a semiconductor with many input/output terminals. The drawback was that it was not compatible with integrated circuits.
上述した従来の半導体集積回路実装方法は、第3図の方
法の場合2次元配置であるため高密度実装化が困難であ
り、第4図の方法の場合、プリント配線基板上の単位面
積当りの接続端子の密度が高くなるために実装が難しく
、又、入出力端子の多い半導体集積回路には対応できな
いという欠点がある.
本発明では、比較的簡単に3次元実装が可能で、高密度
実装化が容易な半導体集積回路パッゲージを提供するこ
とを目的としている.〔課題を解決するための手段〕
本発明の集積回路パッケージは、成形した端子を含む封
入済み半導体集積回路を挿入できる少くとも一端に開口
部を備えた中空部と、該中空部に挿入された複数個の前
記封入済み半導体集積回路のそれぞれの前記端子間と該
端子と前記中空部から外部へ導出された外部端子とを接
続するパッケージ内部端子と、パッケージ内部配線とを
有している.
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
.
第1図は本発明の一実施例の斜視図である.第1図に示
すように、中空パッケージ1は、中空パッケージ1の中
空部に納入される封入済み半導体集積回路の入出力端子
と接続するパッケージ内部端子2及び外部端子3並びに
封入済み半導体集積回路間とパッケージ内部端子2と外
部端子3を接続するパッケージ内部配線4から構成され
ている。In the conventional semiconductor integrated circuit mounting method described above, high-density mounting is difficult in the case of the method shown in FIG. 3 because of the two-dimensional arrangement, and in the case of the method shown in FIG. It is difficult to implement due to the high density of connection terminals, and it also has the disadvantage of not being compatible with semiconductor integrated circuits that have many input/output terminals. An object of the present invention is to provide a semiconductor integrated circuit package that can be relatively easily mounted in three dimensions and that can be easily mounted at high density. [Means for Solving the Problems] The integrated circuit package of the present invention includes a hollow portion having an opening at at least one end into which an encapsulated semiconductor integrated circuit including a molded terminal can be inserted, and an encapsulated semiconductor integrated circuit including a molded terminal inserted into the hollow portion. The package has internal terminals that connect between the terminals of each of the plurality of encapsulated semiconductor integrated circuits and between the terminals and external terminals led out from the hollow portion, and package internal wiring. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view of one embodiment of the present invention. As shown in FIG. 1, the hollow package 1 has package internal terminals 2 and external terminals 3 that are connected to the input/output terminals of the encapsulated semiconductor integrated circuits to be delivered into the hollow part of the hollow package 1, and between the encapsulated semiconductor integrated circuits. and package internal wiring 4 that connects the package internal terminals 2 and external terminals 3.
第2図(a),(b)は第1図の中空パッケージにPL
CCタイプの64kbitスタティックRAMを8ヶ内
蔵した場合の斜視図及びその回路図である。Figures 2 (a) and (b) show the PL in the hollow package in Figure 1.
It is a perspective view and its circuit diagram when eight CC type 64kbit static RAMs are built-in.
第2図(a)に示すように、第1図の開口部5からPL
CCタイプの64kb i tスタティックRAM6を
8ヶ挿入し、64kbitスタティックRAM6の入出
力端子と中空パッケージ1内のパッケージ内部端子2が
接触するようにする。このときパッケージ内部配線4は
、第2図(b冫に示す結線にすると、第2図(a)に示
す中空パッケージ1は、64kX8b i tのスタテ
ィックRAMと.して使用できるようになる。As shown in FIG. 2(a), from the opening 5 in FIG.
Eight CC type 64kbit static RAMs 6 are inserted so that the input/output terminals of the 64kbit static RAMs 6 and the package internal terminals 2 in the hollow package 1 are in contact with each other. At this time, if the package internal wiring 4 is connected as shown in FIG. 2(b), the hollow package 1 shown in FIG. 2(a) can be used as a 64k×8bit static RAM.
つまり、複数の封入済み半導体集積回路を1つの中空パ
ッケージの中に挿入し、共用できる端子及び半導体J[
回路間で完結できる端子を中空パッケージ1内で接続し
、必要最小限の信号を外部端子3から取り出すことによ
り、プリント配線板上に設置した場合に高密度実装を実
現することができる.
〔発明の効果〕
以上説明したように本発明は、封入済み半導体集積回路
の端子形状をした中空部を持ち、かつ、中空部にはめ込
まれる複数個の封入済み半導体集積回路間及び外部端子
を接続する配線を有する集積回路パッケージにすること
により、プリント配線基板上への3次元配置が可能とな
り、プリント配線基板上での接続端子密度を低減し、高
密度実装を容易にすることができるという効果があ今.In other words, multiple encapsulated semiconductor integrated circuits can be inserted into one hollow package and the terminals and semiconductors can be shared.
By connecting terminals that can be completed between circuits within the hollow package 1 and extracting the minimum necessary signals from the external terminals 3, high-density mounting can be achieved when installed on a printed wiring board. [Effects of the Invention] As explained above, the present invention has a hollow part shaped like a terminal of an encapsulated semiconductor integrated circuit, and connects a plurality of encapsulated semiconductor integrated circuits fitted in the hollow part and external terminals. By creating an integrated circuit package with wiring that allows for three-dimensional placement on a printed wiring board, the density of connection terminals on the printed wiring board can be reduced and high-density mounting can be facilitated. Now.
第1図は本発明の一実施例の斜視図、第2図(a),(
b)は第1図の中空パッケージにPLCCタイプの64
kb i tスタティックRAMを8個内蔵した場合の
斜視図及びその回路図、第3図は−従来の集積回路の実
装の一例を示す斜視図、第4図は従来の集積回路の実装
の他の例を示す斜視図である.
1・・・中空パッケージ、2・・・パッケージ内部端子
、3.13.23・・・外部端子、4・・・パッケージ
内部配線、5・・・パッケージ開口部、6・・・64k
bitスタティックRAM、7・・・電源端子、8・・
・GND端子、9・・・チップセレクト端子、10・・
・ライトイネーブル端子、11・・・データ入力及びデ
ータ出力端子、12・・・アドレス入力端子、14.2
4・・・封入済み半導体集積回路、l5・・・パッケー
ジ内部。Figure 1 is a perspective view of one embodiment of the present invention, Figures 2 (a) and (
b) is a PLCC type 64 in the hollow package shown in Figure 1.
Fig. 3 is a perspective view showing an example of a conventional integrated circuit implementation, and Fig. 4 is a perspective view showing an example of a conventional integrated circuit implementation. It is a perspective view showing an example. DESCRIPTION OF SYMBOLS 1...Hollow package, 2...Package internal terminal, 3.13.23...External terminal, 4...Package internal wiring, 5...Package opening, 6...64k
bit static RAM, 7... power supply terminal, 8...
・GND terminal, 9... Chip select terminal, 10...
・Write enable terminal, 11...Data input and data output terminal, 12...Address input terminal, 14.2
4... Enclosed semiconductor integrated circuit, l5... Inside the package.
Claims (1)
きる少くとも一端に開口部を備えた中空部と、該中空部
に挿入された複数個の前記封入済み半導体集積回路のそ
れぞれの前記端子間と該端子と前記中空部から外部へ導
出された外部端子とを接続するパッケージ内部端子と、
パッケージ内部配線とを有することを特徴とする集積回
路パッケージ。a hollow part having an opening at at least one end into which an encapsulated semiconductor integrated circuit including a molded terminal can be inserted; and a space between the terminals of each of the plurality of encapsulated semiconductor integrated circuits inserted into the hollow part; a package internal terminal connecting the terminal and an external terminal led out from the hollow part;
1. An integrated circuit package comprising package internal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1189486A JPH0353559A (en) | 1989-07-21 | 1989-07-21 | Integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1189486A JPH0353559A (en) | 1989-07-21 | 1989-07-21 | Integrated circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0353559A true JPH0353559A (en) | 1991-03-07 |
Family
ID=16242069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1189486A Pending JPH0353559A (en) | 1989-07-21 | 1989-07-21 | Integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0353559A (en) |
-
1989
- 1989-07-21 JP JP1189486A patent/JPH0353559A/en active Pending
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