JPS607152A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS607152A JPS607152A JP58113754A JP11375483A JPS607152A JP S607152 A JPS607152 A JP S607152A JP 58113754 A JP58113754 A JP 58113754A JP 11375483 A JP11375483 A JP 11375483A JP S607152 A JPS607152 A JP S607152A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- cage
- lsi
- package
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関し、特に・ぐツケージに設けら
れるコンタクト部を改良した半導体装置に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a contact portion provided in a shoe cage is improved.
従来の半導体装置としては第１図に示す構造のものが知
られている。即ち１図中の１は半導体素子を収納したパ
ッケージである。このパッケージ１は半導体素子（図示
せず）が設置される四部を有するセラミジク製のノ！ツ
ケージ本体２と、この本体２の凹部に嵌合され半導体素
子を気密に封止するためのキャップ３とから構成されて
いる。また、前記パッケージ１の下面には該・ぐツケー
ジＩ内に収納された半導体素子を外部に接続するための
一ン（コンタクト部）４・・・が設けられている。As a conventional semiconductor device, one having the structure shown in FIG. 1 is known. That is, 1 in FIG. 1 is a package containing a semiconductor element. This package 1 is made of ceramic and has four parts in which semiconductor elements (not shown) are installed. The cage body 2 is composed of a cage body 2 and a cap 3 that is fitted into a recessed portion of the cage body 2 to hermetically seal a semiconductor element. Further, on the lower surface of the package 1, a contact portion 4 is provided for connecting the semiconductor element housed in the shoe cage I to the outside.
しかしながら、従来の半導体装置においては。 However, in conventional semiconductor devices.
内部に収納した半導体素子としてのＬＳＩが多ビン化す
ると、ビン数が増えるために、ピン間隔を狭くするが、
パッケージを大きくする必要がある。ピンの間隔を狭く
することは、当然、物理的なビン配置に限界が生じる。When an LSI as a semiconductor element housed inside has a large number of bins, the pin spacing must be narrowed because the number of bins increases.
The package needs to be larger. Naturally, narrowing the pin spacing places a limit on the physical bin arrangement.
一方、・セラケージ自身を大きくすると、印刷配線板上
に実装する際、実装密度が低下する欠点を招く。On the other hand, if the cell cage itself is made larger, the packaging density will be lowered when it is mounted on a printed wiring board.
本発明はフンタクト部の間隔の短縮化や・（ツケージの
面積増大を招くことなく、パッケージ内に多ビン化した
ＬＳ Ｉ’ｅ収納し得る半導体装置を提供しようとする
ものである。The present invention aims to provide a semiconductor device that can accommodate a multi-bin LS I'e in a package without shortening the interval between contact portions or increasing the area of the package.
本発明は半導体素子（ＬＳＩ）等を収納したパッケージ
の両面にコンタクト部を設け、実質的なビン数を増やす
ことによって、既述した問題を解消してＬＳＩの多ピン
化に対応した半導体素子を得ることを骨子とするもので
ある。The present invention solves the above-mentioned problems by providing contact portions on both sides of a package housing a semiconductor device (LSI), etc., and increasing the actual number of bins, thereby making it possible to create a semiconductor device that is compatible with the increasing number of pins in LSI. The main point is to obtain.
以下１本発明の実施例を第２図を参照して説明する。 An embodiment of the present invention will be described below with reference to FIG.
図中の１１は図示しない多ビン型のＬＳＩを収納した・
ぐツケージである。この・やツケージ１ノはＬＳＩが設
置される凹部を有するセラミック製のノやツケージ本体
１２と、この本体１２の四部に嵌合され、ＬＳＩを気密
に封止するためのキャップ１３とから構成されている。11 in the figure houses a multi-bin type LSI (not shown).
It's a gut cage. This cable cage 1 is composed of a ceramic cable cage body 12 having a recess in which the LSI is installed, and a cap 13 that is fitted into the four parts of the main body 12 to airtightly seal the LSI. ing.
また。Also.
前記・ぐツケージ１ノの上下面の周縁には該・ｆツケー
ジ１１内に収納されたＬＳＩを外部に接続するためのピ
ン（コンタクト部）１４８・・・。At the periphery of the upper and lower surfaces of the cage 1, there are pins (contact portions) 148 for connecting the LSI housed in the cage 11 to the outside.
１４ｂ・・・が突出して設けられている。14b... are provided in a protruding manner.
しかして１本発明の半導体装置はパッケージ１１の上下
面の周縁にコンタクト部としてのピン１４ａ・・・、１
４ｂ・・・を設けているため、従来の同一サイズにした
場合、２倍のビン数を確保できる。その結果、パッケー
ジ１１内に収納したＬＳＩの多ピン化に伴なってビン数
が増大しても、ピン１４ａ・・・、１４ｂ・・・の間隔
を狭くする必要がなく、シかもノ４ツケージ１１の面積
増大も回避できる。したがって、ビ／１４ａ・・・。Therefore, in the semiconductor device of the present invention, pins 14a . . .
4b, etc., it is possible to secure twice the number of bins when the size is the same as in the conventional case. As a result, even if the number of bins increases due to the increase in the number of pins of the LSI housed in the package 11, there is no need to narrow the spacing between the pins 14a..., 14b... 11 can also be avoided. Therefore, Bi/14a...
１４ｂ・・・の間隔を広くできることにより、ショー
ト防止を図ることができ、かつノぐツケージ１ノの面積
増大を回避できることにより、印刷配線板への実装２２
度を向上できる。By widening the interval between 14b..., the show
This makes it possible to prevent mounting on printed wiring boards, and also to avoid an increase in the area of the cage 1.
You can improve your degree.
なお、本発明１ｆＣ係る半導体装置は上記実施例に示す
構造に限らず、第３図（ａ）（ｂ）に示す如く・母ツケ
ーノ１１の上下面の周縁１ｃ ｙｙメタンのコンタクト
部Ｊ４．Ｉ’・・・、１４ｖ・・・を設けた構造にして
もよい。It should be noted that the semiconductor device according to the present invention 1fC is not limited to the structure shown in the above embodiment, but as shown in FIGS. 3(a) and 3(b). A structure may be adopted in which I'..., 14v... are provided.
以上詳述した如く１本発明によればノ（ツケージ内に収
納する半導体素子パ゛多ビン化してもコンタクト部間の
ショート防止や印刷配線板への実装密度の向上を達成し
得る半導体装置を提供できる。As detailed above, the present invention provides a semiconductor device that can prevent short circuits between contact portions and improve packaging density on a printed wiring board even when the number of semiconductor element pins housed in a cage is increased. Can be provided.
第１図は従来の半導体装置を示す斜視図、第２図は本発
明の一実施例を示す半導体装置の斜視図、第３図（ａ）
は本発明の他の実施例を示す半導体装置の斜視図、同図
（ｂ）は同図（ａ）の半導体装置の拡大側面図である。
１１・・・ノぐツケージ、１２・・・ノ臂ツケージ本体
。
１３・・・キャップ、１４ａ、１４ｂ、１４ａ’。
１４ｂ／・・・コンタクト部。FIG. 1 is a perspective view showing a conventional semiconductor device, FIG. 2 is a perspective view of a semiconductor device showing an embodiment of the present invention, and FIG. 3(a)
1 is a perspective view of a semiconductor device showing another embodiment of the present invention, and FIG. 10B is an enlarged side view of the semiconductor device of FIG. 11... Nogutsu cage, 12... Nogutsu cage body. 13... Cap, 14a, 14b, 14a'. 14b/... contact part.
Claims (1)
ジの両面に設けられたコンタクト部とを具備したことを
特徴とする半導体装置。A semiconductor device comprising: a flat cage housing a semiconductor element; and contact portions provided on both sides of the flat cage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58113754A JPS607152A (en) | 1983-06-24 | 1983-06-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58113754A JPS607152A (en) | 1983-06-24 | 1983-06-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS607152A true JPS607152A (en) | 1985-01-14 |
Family
ID=14620279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58113754A Pending JPS607152A (en) | 1983-06-24 | 1983-06-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607152A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62172756U (en) * | 1986-04-21 | 1987-11-02 | ||
| US5041899A (en) * | 1988-06-08 | 1991-08-20 | Fujitsu Limited | Integrated circuit device having an improved package structure |
| US6285079B1 (en) | 1998-06-02 | 2001-09-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device employing grid array electrodes and compact chip-size package |
| KR100664795B1 (en) | 2002-12-30 | 2007-01-04 | 동부일렉트로닉스 주식회사 | Wire Stackable Semiconductor Package and Its Structure |
-
1983
- 1983-06-24 JP JP58113754A patent/JPS607152A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62172756U (en) * | 1986-04-21 | 1987-11-02 | ||
| US5041899A (en) * | 1988-06-08 | 1991-08-20 | Fujitsu Limited | Integrated circuit device having an improved package structure |
| US6285079B1 (en) | 1998-06-02 | 2001-09-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device employing grid array electrodes and compact chip-size package |
| KR100664795B1 (en) | 2002-12-30 | 2007-01-04 | 동부일렉트로닉스 주식회사 | Wire Stackable Semiconductor Package and Its Structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4540226A (en) | Intelligent electronic connection socket | |
| JPS63242696A (en) | Semiconductor-device card | |
| KR970004541B1 (en) | Memory card | |
| JPS60160089A (en) | Connection cartridge for integrated circuit memory card | |
| JPS5858342U (en) | hybrid integrated circuit | |
| JPS62136060A (en) | Semiconductor device | |
| JPS5939087A (en) | Electronic circuit device | |
| JPH01238152A (en) | Semiconductor device | |
| JPS635236Y2 (en) | ||
| JPS5953468U (en) | data card | |
| JPS61107675A (en) | Laminate type pin frame | |
| JPS5832657U (en) | semiconductor equipment | |
| JPS59167041A (en) | Package of integrated circuit | |
| JPH0121629B2 (en) | ||
| JPS614436U (en) | Packages for semiconductor devices | |
| JPS5987841A (en) | Hybrid integrated circuit | |
| JPS58176994A (en) | Electronic circuit | |
| JPS5923747U (en) | semiconductor package | |
| JPS5881952U (en) | Hybrid IC package structure | |
| JPS6354753A (en) | Package | |
| JPS60163749U (en) | Molded dual inline package cage | |
| JPS5954938U (en) | Multi-stage structure of leadless package | |
| JPS60112089U (en) | Socket for semiconductor device | |
| JPS58187151U (en) | High density package | |
| JPS5954952U (en) | semiconductor equipment |