JPH0353711A - Double frequency circuit - Google Patents

Abstract

PURPOSE:To control an input signal twice without use of any inverter for one period by converting a pulse wave of a prescribed period into a sinusoidal wave, inverting the negative polarity of the sinusoidal voltage into a positive polarity and forming a pulse wave with a voltage change based on the waveform. CONSTITUTION:A pulse wave oscillated by an oscillator 11 is converted into a sinusoidal wave by a circuit 13 and a negative polarity of the sinusoidal voltage is inverted into a positive polarity based on a sinusoidal wave sent from a positive polarity forming circuit is to form a waveform with positive polarity only. Then the pulse wave is formed with the voltage change based on the waveform of only the positive polarity. The processing above is repeated to generate a pulse wave bisecting the period of the pulse wave with a prescribed period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of doubling the frequency of a pulse wave using an oscillator that oscillates a pulse wave with a constant period.

[Conventional technology]

The conventional technology will be explained with reference to the drawings.

Conventionally, based on the pulse wave output from an oscillator that oscillates a pulse wave with a constant period, the period of the pulse wave is halved, and the pulse wave oscillated by the oscillator is synchronized with the pulse wave with a constant period. There was no circuit to create.

Therefore, conventionally, when control is performed during one period (hereinafter referred to as one period) that does not include the second rise of a pulse wave of a constant period, control is performed using a circuit as shown in FIG.

The structure of the block diagram of the conventional circuit shown in FIG. 5 will be explained.

Reference numeral 51 in FIG. 5 is an oscillator (hereinafter referred to as an oscillator) that oscillates a pulse wave with a constant period.

52 and 53 are circuits (hereinafter referred to as Philip flops) that control input signals using pulse waves of a constant period. 54 is a circuit (hereinafter referred to as an inverter) for inverting the polarity of an input signal and outputting the same. 55 is an arbitrary input signal (hereinafter referred to as an input signal).

) line.

56 is a pulse wave (hereinafter referred to as C) generated by the oscillator.
It is called the LK signal. ) line. 57 is a signal output by the inverter (hereinafter referred to as a CLK signal).

) line. 58 is the above-mentioned Philip Fulop (
This is the signal (hereinafter referred to as the output ■ signal) line that is output by ■ in the figure. Reference numeral 59 denotes a signal (hereinafter referred to as output ■ signal) line outputted by the above-mentioned Philip flop (53 in the figure).

Next, the timing of the conventional circuit shown in FIG. 5 will be explained using FIG. 6.

61 in FIG. 6 indicates the timing of the input signal line (
55) in FIG. 62 is the timing of the CLK signal line (56 in FIG. 5).

63 is the timing of the output signal line (58 in Figure 5)
It is. 64 is the timing of the CLK signal line (57 in FIG. 5). 65 is the timing of the output 52 signal line (59 in FIG. 5).

Next, the operation of the conventional circuit will be explained using FIG. 6.

Conventionally, when controlling an arbitrary input signal during one cycle of the CLK signal output from an oscillator, first, a Philip flop was used to perform control according to the rising edge of the input CLK signal (a in the figure). (timing), output 61 signal is created (timing b in the figure). Next, the output 6l signal is controlled by the rising edge of the CLK signal using the Philip flop again (timing C in the figure).
, the output ■ signal was being output (timing d in the figure).

[Problem to be solved by the invention]

In the conventional circuit described above, when controlling an arbitrary input signal during one period of the CLK signal output from the oscillator, even if an inverter is used, the control can only be performed twice.

Therefore, when performing control three or more times, there is a drawback that control must be performed in the next cycle of the CLK signal.

[Means to solve the problem]

The structure of the frequency doubler circuit of the present invention includes an oscillator that oscillates a pulse wave with a constant period, a circuit that converts the pulse wave into a sine wave based on the sine wave, and a circuit that converts the sine wave into a sine wave voltage based on the sine wave. It has a circuit that inverts the negative polarity part to the positive polarity part and creates a waveform of only the positive polarity part, and a circuit that creates a pulse wave by changing the voltage based on the waveform of the positive polarity part only. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. No.l
In the figure, 11 is an oscillator, and 12 is a line for propagating the pulse wave (hereinafter referred to as pulse wave) oscillated by 11. ' It is.

13 is a circuit for converting the pulse wave propagated by 12 into a sine wave (hereinafter referred to as a sine wave conversion circuit).

), and 14 is a line for propagating the sine wave (hereinafter referred to as sine wave) converted by 13. l5 is a circuit for inverting the negative polarity part due to the voltage of the sine wave to a positive polarity part based on the sine wave propagated by 14, and creating a waveform of only the positive polarity part. 16 is a line for propagating the waveform in which only the positive polarity portion is formed by 15 (hereinafter referred to as the positive polarity portion). I7 is a circuit (hereinafter referred to as a frequency-divided pulse wave creation circuit) for creating a pulse wave by changing the voltage based on the positive polarity wave propagated by l6;
8 is a line for propagating the pulse wave generated by l7 (hereinafter referred to as a frequency-divided pulse wave). 19 is the above-mentioned sine wave conversion circuit, a positive polarity part creation circuit, a frequency division pulse wave creation circuit, a pulse wave line, a sine wave line, a positive polarity part line, and a frequency division pulse wave. This is a circuit (hereinafter referred to as a frequency divider circuit) consisting of lines.

Next, the operation of the circuit configured in this manner will be explained.

FIG. 2 shows the timing on the lines of the block diagram shown in FIG.

In Figure 2, 21 is a constant period pulse wave (1 in Figure 1).
This shows the timing of 2).

22 indicates the timing of the sine wave (14 in FIG. 1). 23 indicates the timing of the positive polarity wave (16 in FIG. 1). 24 indicates the timing of the frequency-divided pulse wave (18 in FIG. 1).

If the maximum voltage of a constant period pulse wave is Vcc (V), create a sine wave 22 based on the pulse wave with a maximum voltage of 10 Vcc - (V) and a minimum voltage of 11 (■). . (22 in Figure 2) Next, the negative polarity part [0 (V)
to 11 (■)] to two positive polarity parts, and create a waveform of only the positive polarity part.

(23 in FIG. 2) Next, a pulse wave is created by changing the voltage based on the waveform of only the positive polarity portion. (24 in Figure 2) In other words, when the voltage of only the positive polarity part changes from 0 (■) to +Vcc - (■) (timing 2 of a in Figure 2), the voltage of the pulse wave to be created is + ■. C (V) (timing a' in Figure 2). Also, when the voltage of only the positive polarity part changes from -1 (■) to O (v) (timing b in Figure 2), the pulse wave to be created is set to 0 (V) (second (timing b' in the figure).

Therefore, by repeating the above steps, it is possible to create a pulse wave in which the period of a constant period pulse wave is divided into two.

FIG. 3 is a block diagram showing an example of application.

In FIG. 3, 31 is an oscillator. 32 is a frequency doubler circuit. 33 is Philip Fulop. 34 is an input signal line. 35 is a CLK signal line oscillated by the oscillator. 36 is a half CLK signal line output from the frequency doubling circuit. 37 is
This is the output signal line output from the above-mentioned Philip flop.

Next, the operation of the device configured in this manner will be explained.

FIG. 4 shows the timing on the lines of the block diagram shown in FIG.

41 in FIG. 4 indicates the timing of the input signal (34 in FIG. 3). 42 is the CLK signal (35 in FIG.
) indicates the timing.

43 indicates the timing of the half CLK signal (36 in FIG. 3). 44 indicates the timing of the output signal (37 in FIG. 3).

First, a half CLK signal is created using a frequency doubler circuit based on a CLK signal oscillated by an oscillator. Next, using a Philips flop, the input signal is controlled by the rising edge of the half-CLK signal (a1 and a in the figure) to create an output signal (timing b1 and b in the figure).

〔Effect of the invention〕

As explained above, according to the present invention, the input signal can be controlled twice during one cycle of the CLK signal without using an inverter. Furthermore, if a frequency doubler circuit and an inverter are used to create the same structure as the conventional circuit, the input signal can be controlled four times during one cycle of the CLK signal.

Therefore, when a plurality (n) of frequency doubling circuits are used and a plurality (n) of inverters are similarly used, control can be performed as many times as the equations shown below.

X = 2”’ (1 set)

[Brief explanation of drawings]

FIG. 1 is a block diagram of the frequency dividing circuit according to the present invention, FIG. 2 is a timing diagram on the line in FIG. 1, FIG. 3 is a block diagram of an embodiment using the frequency dividing circuit, and FIG. The figures are a timing diagram on the line in FIG. 3, FIG. 5 is a block diagram of the prior art, and FIG. 6 is a timing diagram on the line in FIG. 1... Oscillator, 2... Pulse wave line, 3... Conversion circuit to sine wave, 4...
Sine wave line, 5... Positive polarity section creation circuit, 6
...Positive polarity line, 7... Frequency division pulse wave creation circuit, 8... Frequency division pulse wave line,
9... Frequency divider circuit, 2l... Pulse wave line, 22... Sine wave line, 23...
・Positive polarity line, 24... Frequency division pulse wave line, 3l... Oscillator, 32... Frequency doubler circuit, 33... Philip flop , 34...
...Input signal, 35...CLK signal, 36
....CLK signal, 37 ....output signal,
41... Input signal, 42... CLK signal, 43... CLK signal, 44... Output signal, 51... Oscillator, 52...Philip Fulop, 53...Philip ゜・
Fluff゜, 54... Inverter, 55...
...Input signal, 56...CLK signal, 57.
...CLK signal, 58...Output ■signal,
59...Output ■signal, 6l...Input signal, 62...CLK signal, 63...Output ■signal, 64...CLK Signal, 65...
・Output■signal.

Claims (1)

[Claims] An oscillator that oscillates a pulse wave with a constant period, a circuit that converts the pulse wave into a sine wave, and a circuit that uses the sine wave to reverse the negative polarity part of the voltage of the sine wave to the positive polarity part. A frequency doubling circuit characterized by having a circuit for creating a waveform of only the positive polarity part, and a circuit for creating a pulse wave by changing the voltage based on the waveform of only the positive polarity part.