JPH0355850B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a debugging method in a program development apparatus.

Prior Art A conventional program development device debugs a program by connecting a plurality of emulators in parallel to one main program development device, each of which is operated by a clock signal of a different cycle. However, in production systems connected to emulators, it is necessary to break the emulators almost synchronously to debug the program, but since the clock signal cycles of each emulator are different, There was a problem in that it was not possible to debug programs on multiple emulators at the same time. In addition, in a system in which the main program development device and multiple emulators are connected in a linked manner via a data line, and each emulator is operated by break data transmitted via this data line, the transmitted break data may be Since the break processing of the emulators is executed sequentially based on the processing time, the processing time of each emulator is delayed, making it impossible to break each emulator synchronously.

OBJECTS OF THE INVENTION An object of the present invention is to provide a debugging method for a program development apparatus that solves the above-mentioned conventional drawbacks.

Example This will be explained below with reference to the drawings.

In FIG. 1, a reference host 1 operates in a computer language, and its outputs are connected in a loop to a plurality of emulators 2, 3, and 4, respectively. The final stage output of the emulator 4 is connected back to the input side of the reference host 1 in the form of a link. These reference host 1 and emulators 2, 3, and 4 have photocouplers and are connected by two optical fiber cables OF1 and OF2. Of the optical fiber cables OF1 and OF2, one line is used as a data bus line, and the other line is used as a clock bus line. still,
Target devices 5, 6 and 7 are connected to the emulators 2, 3 and 4, respectively.

In FIG. 2, the main bus includes a main control 9 for operating the system, a memory bank 10, a printer 11, an interface 12,
A keyboard 13, ROM 14, RAM 15, and optical transmitter/receiver 16 are connected and configured. Further, the keyboard 13, composite 17 and CRT 18 are connected to the console.

In FIG. 3, the emulation bus 20 of each emulator 2, 3, and 4 includes a CPU 21 and a ROM.
23, RAM 24, control section 25, and optical receiving section 26 are connected to each other. A target 27 is connected to the control section 25. Further, two optical fiber cables OF1 and OF2 are connected in a link manner to the optical receiving section 16 on the host side and the optical receiving section 26 on each emulator side.

Next, in FIG.
A common bank with byte storage addresses is provided. Incidentally, within this common bank, the rewritable area is an area corresponding to each emulator. Data sent from this common bank is always sent sequentially from start to end to each emulator 2,
It is sent to common banks 3 and 4. The data received by each emulator 2, 3, 4 is constantly compared with data in the common bank to monitor for data errors.

The reference host 1 and emulators 2, 3, and 4, which are linked in a loop in this way, can monitor the presence or absence of requests from others by constantly comparing with the area of the common bank, and can monitor the presence or absence of requests from others by constantly comparing the area of the common bank with By writing a request to , it is possible to transmit its own request to other emulators 2 , 3 , 4 and the reference host 1 . That is, when a request for data transmission is generated from the reference host 1 to the emulator 2, when the request is written to the host area of the common bank of the reference host 1, each emulator 2,
After the host request is transmitted to the common banks 3 and 4, the reference host 1
Since the request is returned to the side, a comparison is made between the request written to the host area of the common bank and the returned request. This allows you to confirm the written request. Further, after confirming that the request is directed to itself, the emulator 2 writes the processing for the written request into the area of the emulator 2 in the common bank. As a result, the processing data is transmitted to the emulator 2 area of the common bank of the reference host 1. As a result, the reference host 1
The emulator 2 can check the processing for the request. Furthermore, after the processing data has been transmitted to its own area after going around the link, the emulator 2 compares the returned processing data with the processing data written in its own area to confirm the processing state.

Next, as the optical fiber cable of the present invention, a dedicated clock way is linked in addition to the data way.

The clock signal transmitted via this clock way is used as a clock signal for data acquisition by each emulator 2, 3, and 4, and the data acquisition and transmission of each emulator 2, 3, and 4 is controlled by this clock signal. Ru.

That is, as shown in FIG. 5, when the reference host 1 breaks the emulator 2 synchronously and the emulator 2 is broken, the clock signal changes to LOW and the CPU 21 of the emulator 2
is halted. As a result, the reference host 1 detects that the CPU 21 of the emulator 2 is halted, and the clock signal of the reference host 1 is changed to LOW. This allows emulators 3 and 4 to
The CPU 21 is also halted substantially synchronously. This allows each emulator 2, 3, and 4 to be broken substantially synchronously. After confirming that each emulator 2, 3, and 4 has been broken, the reference host 1 resets the clock signal and enables data reception.

As shown in FIG. 5, after the reference host 1 sends data, there is a byte delay depending on the number of emulators 2, 3, and 4 arranged until the data is received. By halting the third and fourth CPUs 21, it is possible to break in a substantially synchronized state.

Therefore, in this embodiment, the reference host 1 and each emulator 2, 3, 4 are connected using two optical fiber cables.
Connected like a link by OF1 and OF2,
By dedicating one of them to the clock, the CPUs 21 of each emulator 2, 3, and 4 can be halted and broken almost synchronously.

Effects of the Invention As explained above, the present invention provides a program development device in which a main program development device and a plurality of emulators are connected in a loop through two optical fiber cables. One system is a data transmission cable, and the other system is a clock-only cable, and this is a debugging program development device that can break multiple emulators almost synchronously using the clock signal transmitted by this clock-only cable. It's a method.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing the link status between the main program development device and each emulator, Fig. 2 is a block diagram of the main program development device, Fig. 3 is a block diagram of each emulator, and Fig. 4 is an explanatory diagram showing the common bank. FIG. 5 is an explanatory diagram showing the operating state. In the figure, 1 is the reference host as the main program development device, 2, 3, and 4 are emulators, OF1, OF2
is a fiber optic cable.

Claims (1)

[Scope of Claims] 1. In a program development device in which a main program development device and a plurality of emulators are connected in a loop through two optical fiber cables, one of the two optical fiber cables is connected to one of the two optical fiber cables. A debugger for a program development device characterized in that one line is a data transmission cable, and the other line is a clock-only cable, and a plurality of emulators can be broken almost synchronously by a clock signal transmitted by the clock-only cable. Method.