JPH0355879B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse input scanning method in a pulse integration device.

[Prior art]

Conventionally, regarding this type of technology, see the Oki Electric Catalog "Standard large-capacity remote monitoring and control equipment", LG3364,
There is one disclosed in 1984.

FIG. 2 is a diagram showing a pulse input circuit in a conventional pulse integration device. In the same figure, 1-
1,...,1-n are external devices NO-1,...,NO-
A photocoupler 2 is used to electrically isolate n and the adder circuit 3, and 2 is a power supply dedicated to the interface. Pulses P1,..., Pn from external devices NO-1,..., NO-n are transmitted through photocouplers 1-1,...,
1-n to the adder circuit 3. Since the pulse input circuits that input pulses from external devices NO-1 to NO-n to the addition circuit 3 have substantially the same configuration, the pulse input circuit that inputs pulses from external device NO-1 will be described here. . The pulse input circuit includes the photocoupler 1-1, resistors R1, R2, diode D1, capacitor C1, etc., and the plus and minus terminals of the interface power supply 2 are connected to the plus and minus terminals of the power supply terminal I. power is supplied.

When the input pulse P1 is input from the external device NO-1, the photocoupler 1-1 is turned on, and the input pulse P1 is input to the adder circuit 3. The pulse input circuit with the above configuration uses external devices NO-1 to NO-
They are provided corresponding to the number n. Incidentally, R3 is a pull-up resistor for the phototransistors constituting the photocouplers 1-1 to 1-n.

[Problem that the invention seeks to solve]

However, in the pulse input circuit with the above configuration, assuming that all pulses from external devices NO-1 to NO-n are input simultaneously, the capacity required to drive all photocouplers 1-1 to 1-n is limited. A power supply 2 dedicated to the interface must be prepared, and the larger the number of pulse input circuits, the larger the capacity of the power supply dedicated to the interface must be.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a pulse input scanning method in a low-power pulse integration device that reduces power consumption and reduces the load on the interface-dedicated power supply.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a pulse integrator equipped with an adder circuit, a plurality of pulse input circuits for inputting a plurality of pulses to be supplied to the adder circuit, and an interface dedicated power supply circuit. Turns on/off the power supplied to the input circuit from the interface dedicated power supply circuit.
The circuit includes an ON/OFF circuit for storing pulses from the input circuit, a pulse primary memory circuit for storing pulses from the input circuit, and a scanning circuit.
The device was configured to operate the ON/OFF circuit to turn the power ON/OFF, and to operate the pulse primary memory circuit to store the input pulse in the pulse primary memory circuit.

[Effect]

By configuring as described above, the scanning circuit periodically turns on and off the power of the pulse input circuit, so compared to the conventional pulse input circuit that constantly turns on the power of the pulse input circuit, the power supply circuit dedicated to the interface is The load can be significantly reduced.

〔Example〕

FIG. 1 is a circuit diagram showing the configuration of a pulse input circuit in a pulse integration device according to the present invention. In this figure, parts given the same reference numerals as those in FIG. 2 indicate the same or equivalent parts.

In FIG. 1, 4-1,..., 4-n are switches for turning on/off the power of each pulse input circuit equipped with photo couplers 1-1,..., 1-n, and 5-
1,...,5-n are inverters that invert the input pulses P1,...,Pn, 6-1,...,6-n are pulse primary memory circuits consisting of D-type flip-flops, and 7-1,...,7-n are pulse primary memory circuits consisting of D-type flip-flops. 8 is an AND circuit, and 8 is a scanning circuit. The switches 4-1 to 4-n provide the photocoupler power supply scanning signals HP1,
..., ON/OFF controlled by HPn. Since the configuration of each pulse input circuit is substantially the same, the pulse input circuit to which the pulse signal P1 is input from external device NO-1 will be described here. The input terminal IN-1 to which the pulse signal P1 is input is connected to the photodiode 1-1 of the photocoupler 1-1 via the circuit protection diode D1 and the signal delay capacitor C1.
It is connected to the cathode side of 1a. Photocoupler 1
The anode side of photodiode 1-1a of photodiode 1-1 is connected to switch 4-1 via current-limiting resistors R2 and R3. The other end of the switch 4-1 is connected to the positive terminal _I1 side of the interface dedicated power supply circuit 2. The collector side of the phototransistor 1-1b of the photocoupler 1-1 is connected to the inverter 5-1 via a pull-up resistor R3, and the output side of the inverter 5-1 is connected to the D terminal of the pulse primary memory circuit 6-1. Connected. The pulse input valid signal PT1 of the scanning circuit 8 is input to the AND circuit 7-1, and the AND circuit 7-1 calculates the logical product of the pulse input valid signal PT1 from the scanning circuit 8 and the clock signal Φ. It's summery.
The output side of the AND circuit 7-1 is connected to the clock terminal of the pulse primary memory circuit 6-1. The output terminal Q of the pulse primary memory circuit 6-1 is connected to the adder circuit 3, and the output signal DP1 is connected to the adder circuit 3.
is input. The pulse input circuit with the above configuration is an external device NO-1 to NO-n that outputs input pulses.
are provided corresponding to the number of The scanning circuit 8 sequentially operates the switches 4-1 to 4-n based on the photocoupler power supply scanning signals HP1 to HPn, and connects the input terminal IN-.
Photocoupler 1-1~ supplied from interface dedicated power supply circuit 2 connected to 1~IN-n
Turn on power supplies 1-n in sequence. Photocoupler power supply scanning signals HP1 to HPn from the scanning circuit 8, which sequentially turn on the power to the photocoupler 1-1 to 1-n, are synchronized with pulse input valid signals PT1 to PT2, which will be described later. ~1-n power-on timing and pulse primary memory circuit 6-1
The timing at which the clock signal is supplied to the clock signals 6-n is the same. Pulse signals P1 to Pn are external devices
When input from NO-1 to NO-n, photo couplers 1-1 to 1-n turn ON in synchronization with the photo coupler power supply scanning signals HP1 to HPn of the connected photo couplers 1-1 to 1-n. . When the photocouplers 1-1 to 1-n turn on, the output signals are inverted and level-converted by the inverters 5-1 to 5-n (converted from logic level "0" to "1"). After, AND circuit 7-1~
A clock signal .PHI. is supplied through 7-n and is stored in the pulse primary memory circuits 6-1 to 6-n which are in an active state. When the power scanning of the photocouplers 1-1 to 1-n is completed, the pulse primary memory circuits 6-1 to 6-n
The supply of the clock signal 6-n is stopped and that state is maintained. FIG. 3 is a timing chart of the pulse input signal P1, the photocoupler power supply scanning signals HP1,..., HPn, the pulse input valid signals PT1,..., PTn, and the output DP1 of the pulse primary memory circuit. As shown in the figure, the pulse input signal P1 is transmitted to the pulse primary memory circuit 6-1 by the photocoupler power supply scanning signal HP1 and the pulse input valid signal PT1.
The state is held until the end of scanning.

As explained above, by configuring the pulse input circuit in the pulse integration device, the scanning circuit 8 is used to scan the power supply of the photocouplers 1-1 to 1-n and control the pulse primary memory circuits 6-1 to 6-n. Therefore, the interface dedicated power supply circuit 2 required to drive the pulse input circuit only needs to have enough power supply capacity to drive the pulse input circuit for one pulse signal input in the pulse input circuit of the conventional pulse integration device. become.

〔Effect of the invention〕

As explained above, according to the present invention, the output signal of the scanning circuit operates the ON/OFF circuit and also operates the pulse primary memory circuit, so that the power supply capacity supplied to the pulse signal input circuit is small. This makes it possible to downsize the power supply circuit dedicated to the interface. In addition, with the reduction in power consumption, it becomes easier to achieve uninterrupted power, and excellent effects such as being able to prevent pulse information from being lost during a power outage can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a pulse input circuit in a pulse integration device according to the present invention, FIG. 2 is a circuit diagram showing a pulse input circuit in a conventional pulse integration device, and FIG. 3 is an operation of the circuit shown in FIG. 1. This is a timing chart to explain. In the figure, 1-1 to 1-n...photocouplers, 2...
...Interface dedicated power supply circuit, 3...Addition circuit, 4-1 to 4-n...Switch, 5-1 to 5-
n...inverter, 6-1 to 6-n...pulse primary memory circuit, 7-1 to 7-n...AND circuit,
8...Scanning circuit.

Claims (1)

[Claims] 1. In a pulse integration device comprising an adder circuit, a plurality of pulse input circuits that input a plurality of pulses to be supplied to the adder circuit, and an interface-dedicated power supply circuit, the interface-dedicated power supply circuit is connected to the plurality of pulse input circuits. The circuit includes an ON/OFF circuit that turns on and off power supplied from the input circuit, a pulse primary memory circuit that stores pulses from the input circuit, and a scanning circuit. along with operating the
A pulse input scanning method, characterized in that the pulse input scanning system operates the pulse primary memory circuit.