JPH046310Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a trigger generation circuit used in television broadcasting equipment and the like.

A conventional trigger circuit of this type had a configuration as shown in the block diagram of FIG. That is, the trigger signal generated by the external master trigger generation circuit 1 is output from its trigger output terminal 2, and is output from the trigger input terminal 13 of each of the plurality of units 10, 20, 30, 40 provided within the shelf board 100. , 23, 33, and 43, and multiple units 1 can be connected by one trigger output signal.
All operations 0, 20, 30, and 40 were performed at the same timing. In this case, the triggers of the trigger input terminals 13, 23, 33, 43 of the units 10, 20, 30, 40 may fail due to a failure of the master trigger circuit 1 or a disconnection between the trigger output terminal 2 and the trigger input 101 of the shelf board 100. The drawback was that all units stopped operating when the signal was cut off. In addition, as this type of trigger circuit, as shown in the block diagram of FIG. 2, there is a case where a plurality of units 10, 20, 30, 40 are each provided with a trigger generation circuit 11, 21, 31, 41. In this case, the operation of all units will not stop at the same time due to a failure of the trigger generation circuit, but it is not completely safe against failure of the trigger generation circuit, and in this case, the timing of each trigger will not be aligned. There was a drawback that all units did not operate in the same way.

An object of the present invention is to eliminate these drawbacks, to provide a trigger circuit that is operable even when some trigger generation circuits fail and whose trigger timing is aligned.

The configuration of the present invention is that in a trigger circuit in which a trigger signal from a main trigger generation circuit is connected to a plurality of units, each of the plurality of units has a sub-trigger generation circuit that generates a trigger signal in synchronization with the trigger signal. The output of the sub-trigger generation circuit and the output of the main trigger generation circuit are connected in parallel, and the OR output thereof is connected to each of the units.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention. This embodiment differs from the conventional configuration in that a plurality of units 10, 20, 30, 40 are each provided with sub-trigger generation circuits 11, 21, 31, 41. These sub-trigger generation circuits 11, 2
Each trigger signal generated from 1, 31, and 41 is an open collector output and is sent to the sub trigger output terminal 1.
2, 22, 32, and 42, respectively. On the other hand, the trigger signal generated from the external master trigger generation circuit 1 is also an open collector output, and is output from the trigger output terminal 2 and sent to the interior of the shelf 100 via the trigger input terminal 101 of the shelf 100. Multiple units 1
0, 20, 30, 40 sub trigger output terminals 1
Trigger signals output from 2, 22, 32, 42 are wire-OR connected to multiple units 1.
0, 20, 30, 40 trigger input terminals 1
3, 23, 33, and 43.

FIG. 4 shows each operation waveform diagram of FIG. 3. Figure 4a shows external master trigger generation circuit 1
master trigger pulse output signal generated from,
Fig. 4 b, c, d, e shows each unit 10, 20,
30, 40 sub-trigger generation circuits 11, 21,
The sub-trigger pulse output signals generated from 31 and 41 are assumed to be the sub-trigger pulse output signals generated from 31 and 41.

Now, each of these trigger output pulses is wired OR connected, so the trigger input terminals 13, 23, 33, and 43 of each unit are
As shown in Fig. 4 f, Fig. 4 a, b, c, d,
The OR output of the trigger signal of e is supplied,
This trigger signal causes multiple units 10, 2 to
All operations 0, 30, and 40 are performed at the same timing.

If the external master trigger generation circuit 1 fails or the connection between the trigger output terminal 2 and the trigger input 101 of the shelf board 100 is disconnected, and the master trigger output signal is disconnected,
The OR outputs of the sub-trigger output signals shown in FIG. 4b, c, d, and e are supplied to the trigger input terminals 13, 23, 33, and 43, respectively. 30,40
All operations are performed at the same timing. Further, if any signal of the sub-trigger generation circuits is disconnected, the OR output of the trigger output signals of the remaining sub-trigger generation circuits becomes the trigger output.

In this way, according to the present invention, if even one of the master trigger generation circuit and multiple sub-trigger generation circuits is operating, all units can operate, and there is no problem with the failure of the trigger generation circuit. becomes.

As explained above, in the present invention, by supplying trigger signals in parallel, it is possible to obtain a trigger circuit that is completely safe against failures in the trigger generation circuit.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a conventional trigger circuit, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIGS. 4a to 4f are operational waveform diagrams of FIG. 3. In the figure, 1... Master trigger generation circuit, 2... Master trigger output terminal, 10, 2
0, 30, 40...unit, 11, 21, 3
1,41...Sub trigger generation circuit, 12,2
2, 32, 42...Sub trigger output terminal, 1
3, 23, 33, 43, 101...Trigger input terminal, 100...Shelf board.

Claims (1)

[Scope of utility model registration request] In a trigger circuit where the trigger signal from the main trigger generation circuit is connected to multiple units,
Each of the plurality of units is provided with a sub-trigger generation circuit that generates a trigger signal in synchronization with the trigger signal, and the outputs of these sub-trigger generation circuits and the output of the main trigger generation circuit are connected in parallel to generate a logical sum. A trigger circuit characterized in that an output is connected to each of the units.