JPH0357228A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a gate input capacity and an external parasitic resistance of an HJFET by a method wherein a low-concentration n-type AlGaAs layer is formed on a surface layer directly under a gate electrode of an n-type AlGaAs electron supply layer on which a Schottky gate electrode is formed. CONSTITUTION:An HJFET is provided with the following: an undoped GaAs layer 2 which has been formed on a semiinsulating GaAs substrate 1; and an N-type AlGaAs layer 3 which has been formed by forming a heterojunction on the layer. An electron accumulation layer which is generated in the GaAs layer 2 along a hetero-junction interface and whose electron mobility is high is used as a conductive channel. By this constitution, a low-concentration n-type AlGaAs layer 8 is formed on a surface layer directly under a gate electrode 9 of the n-type AlGaAs electron supply layer 3 on which a Schottky gate electrode 9 is formed. This low concentration is realized by restoring a crystal by a plasma treatment by a Freon-based reactive ion etching operation of only the surface layer directly under the gate electrode 9 and only in a local region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a compound semiconductor device, and particularly to a semiconductor device having a field effect type high electron mobility transistor using a 1V group compound semiconductor.

[Conventional technology]

In conventional semiconductor devices, the n-type AfflGaAs electron supply layer and the n-type GaAs layer provided above the substrate have a uniform concentration gradient in the plane or a change in the mixed crystal ratio composition in the depth direction. There have been no reports of the high electron mobility transistor in which the concentration is reduced in-plane, particularly in the surface layer of the local region immediately below the gate electrode of the field effect transistor, and the gate electrode is formed without reducing the concentration in the external region. Not yet.

[Problem to be solved by the invention]

In the conventional field-effect high mobility transistor (hereinafter referred to as HJF'ET) described above, the n-type AuGaAs electron supply layer or the n-type GaAs cap layer directly under the Schottky gate electrode are aligned in the same depth direction within the substrate surface. It has various concentrations. Here, IEEE Transactions on Electron Devices (IEEE Tran
actions onElectron Device
es) Volume ED-30, 1983, page 207, or
Solid State Electron (Solid-St
ate Electron), Vol. 28, 1985, p. 997, the mutual conductance gm or transmission resistance Rm of the HJFET is expressed as follows.

However, Rs: source resistance, ε: dielectric constant, d: gate-channel distance, Lg: gate length, Id. ．． ．． : drain saturation current, μ: mobility, and the cutoff frequency fT is generally expressed as follows.

However, gmo is the intrinsic transfer conductance ignoring the source resistance, and Cgs is the gate input capacitance.As can be seen from the above equation, in order to improve the high frequency characteristics such as the cutoff frequency fT of the HJFET, the mutual conductance gm must be large and the gate input capacitance must be large. Although it is necessary to reduce Cgs, since both are in a trade-off relationship with respect to the gate-channel spacing, it is considered necessary to improve other parameters for a given gate length.

Therefore, in the above-mentioned HJFET with a uniform concentration within the substrate surface, when a gate electrode is formed to have a desired threshold voltage, the gate input capacitance Cgs and The mutual conductance gm and the source resistance Rs also change with the threshold voltage, and especially when creating an enhancement type HJFET, etc., there is a drawback that an increase in the source resistance Rs near the Schottky gate is unavoidable. Furthermore, in the conventional structure, the control factor of capacitance and the control factor of mutual contagance gm at the same gate length are almost determined by the distance between the gate and channel, so there remains a problem in their controllability. Furthermore, the gate breakdown voltage and forward diode characteristics of the HJFET are also degraded by forming the gate electrode on highly doped n-type AβGaAs or heavily doped n-type GaAs, which is unfavorable in terms of device characteristics.

[Means to solve the problem]

In the present invention, in order to solve the problems of the prior art, the HJFE
The n-type AJ7GaAs layer and n-type Ga directly below the gate electrode of T.
The transistor has a transistor structure in which only the very surface layer of the As layer is locally reduced in concentration in the same depth direction, and the other regions are not reduced in concentration.

As a means of embodying the HJFET of the present invention, plasma treatment by freon-based reactive ion etching (hereinafter referred to as RIE) or hydrogen plasma treatment is performed only on the gate electrode shape region before the Schottky gate electrode shape is formed. A method for eliminating n-type carriers in the surface layer of AI2GaAs or n-type GaAs may be mentioned. This method involves performing Freon-based RIE under a predetermined bias on an n-type ■-V group compound semiconductor to annihilate n-type carriers over a predetermined depth, and hydrogen plasma on a silicon-doped n-type ■-V group compound semiconductor. It is based on the general fact that the treatment eliminates n-type carriers to a desired depth.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 1(a), a non-doped GaAs layer 2 and an n-type Ai7GaA layer are formed on a semi-insulating GaAs substrate l.
An epitaxial layer in which an n-type GaAs cap layer 4 making ohmic contact with the s-layer 3 is successively laminated is formed by MBE. The HJFET is a semiconductor device whose conductive channel is an electron storage layer with high electron mobility generated in the non-doped GaAs layer 2 along the heterojunction interface, and the N-type AlGaAs layer 3 directly under the gate is in a depleted state.

After separating the active layer region from the substrate by mesa etching, which is usually performed in GaAs field effect transistors, AuGe/Ni/Au is etched in the source/drain region.
The ohmic electrode 5 is shaped by a resist lift-off method and heat treated to form a contact. Thereafter, a silicon oxide film 6 is deposited over the entire surface of the substrate, and a gate formation pattern is formed using a photoresist film 7.

Next, as shown in FIG. 1(b), using the photoresist film 7 as a mask, the silicon oxide film 6 is wet-etched with HF or the like to open a gate formation region, and the n-type GaAs cap layer 4 is etched with H 2 S. Etching is performed to the surface of n-type Aj2GaAs3 using a crystal etchant such as a mixed solution of O 2 and H202 to obtain a desired threshold voltage.

Next, Freo-based RIE of iH F 3 gas etc. was performed using the method described in the section 0.
Using the photoresist film 7 as a mask, only the region where the gate shape is to be formed is processed by controlling the RIE power and RIE processing time gas partial pressure, thereby forming the low concentration layer 8 to a predetermined depth. This treatment may be performed in the process of processing the silicon oxide film 6, and then wet etching the n-type GaAs cap layer 4 using the above-mentioned crystal etchant.

Next, as shown in FIG. 1(c), A1 or Ti/Au was
Alternatively, the gate electrode 9 made of Ni/AA is formed after monitoring that the desired threshold voltage is achieved.

Here, the desired threshold voltage can be controlled by monitoring the current between the source and drain using a monitoring element in which the source and drain ohmic electrodes are provided in a region separate from the main element, or by using the same as above. H with expanded gate fenestration area
The plasma RIE is performed while being evaluated by a method of monitoring the threshold voltage using a liquid Schottky such as G-Schottky.

Next, as shown in FIG. 1(d), the silicon oxide film 6 is removed, and an insulating film 10 made of a silicon oxide film or a silicon nitride film as a passivation film is deposited using a GaAs MESFET manufacturing method to form an ohmic electrode. After opening holes on the substrate 5, the Ti/Pt/Au is processed by ion milling or the like to form a source electrode 11a and a drain electrode 1b.

In this example, the temperature was 300°C to 500°C after forming the gate electrode.
It is also possible to perform heat treatment.

FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention.

As shown in FIG. 2(a), after forming up to the ohmic electrode by the same process as in the first embodiment shown in FIG. 1(a), a silicon oxide film l2 is deposited on the entire surface to form a gate electrode. A formation opening is provided, and a silicon nitride film 13 is deposited on the surface including the opening.

Next, as shown in FIG. 2(b), the anisotropic Freon yarn R
Etching back is performed by IE to provide a sidewall portion 14 leaving the silicon nitride film 13 only on the sidewall of the opening of the silicon oxide film 12, and a low concentration layer 8 is formed using the plasma treatment. In this embodiment, after the plasma processing, the current monitor and threshold voltage monitor shown in the first embodiment are measured, and then the threshold voltage is controlled to the optimum threshold voltage.
It is also possible to adjust by heat treatment in a nitrogen atmosphere or hydrogen atmosphere at 00°C to 500°C.

Next, as shown in FIG. 2(c), a WxSix/Ti/Au layer for forming a gate electrode and a Ti/Ti layer are formed on the surface including the opening.
A /Pt/Au layer is deposited and processed by ion milling or RIE to form the gate electrode 9.

Next, as shown in FIG. 2(d), after coating the side wall portion l4 and the silicon nitride film 13, the insulating film 10, the source electrode 11 & the drain electrode 1lb are formed.
Be wary of JFET.

〔Effect of the invention〕

As explained above, in the present invention, only the surface layer and local region directly under the Schottky gate electrode of the HJFET is subjected to plasma dehydration using Freon-based RIE or hydrogen plasma treatment, etc., and then subjected to heat treatment at 300°C to 500°C to recover crystals. , by lowering the concentration, it is possible to create a HJFET structure in which the external region other than directly under the gate electrode is not lowered in concentration.

This device structure has the effect of simultaneously achieving reductions in gate input capacitance and external parasitic resistance.

[Brief explanation of drawings]

FIGS. 1(a) to (d) and FIGS. 2(a) to (d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining the manufacturing method of the first and second embodiments of the present invention. It is. 1...Semi-insulating GaAs substrate, 2...
...Non-doped GaAs layer, 3--n-type AnGaA
s layer, 4...n-type GaAs layer, 5...
Ohmic electrode, 6...Silicon oxide film, 7.
... Photoresist film, 8 ... Low concentration layer, 9 ... Gate electrode, 10 ... Insulating film, lla ... Source electrode, llb・・・・・・
Drain electrode, 12...Silicon oxide film, 13
...Silicon nitride film, l4...Side wall part.

Claims (1)

[Claims] Non-doped GaAs on a semi-insulating GaAs substrate
layer and a N layer provided by forming a heterojunction on the GaAs layer.
type AlGaAs layer, in which a conductive channel is an electron storage layer with high electron mobility generated in the GaAs layer along the heterojunction interface, in which an n-type AlGaAs layer on which a Schottky gate electrode is formed; Low concentration n-type AlGa provided in the surface layer directly under the gate electrode of the electron supply layer
A semiconductor device characterized by having an As layer.