JPH0357623B2 - - Google Patents
Info
- Publication number
- JPH0357623B2 JPH0357623B2 JP60214852A JP21485285A JPH0357623B2 JP H0357623 B2 JPH0357623 B2 JP H0357623B2 JP 60214852 A JP60214852 A JP 60214852A JP 21485285 A JP21485285 A JP 21485285A JP H0357623 B2 JPH0357623 B2 JP H0357623B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- resin sealing
- sealing part
- sealed
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/411—Chip-supporting parts, e.g. die pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/811—Multiple chips on leadframes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は、樹脂封止型半導体装置に関し、さら
に詳しくは第一樹脂封止をした後第二樹脂封止を
する二重モールド形式の半導体装置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a resin-molded semiconductor device, and more particularly to a double-molded semiconductor device in which a first resin seal is performed and a second resin seal is performed. Regarding.
［発明の技術的背景］
半導体チツプを搭載したリードフレームを放熱
フインとともに樹脂封止をする場合、素子搭載部
と放熱フイン間で電気絶縁と熱放散が両立するよ
うに、両者の間隔を所望の値に制御してトランス
フア成形をすることは極めてむずかしい。特に、
複数の半導体チツプを搭載したリードフレームで
は、大形となるために成形中湾曲して、放熱フイ
ンに対して１つの素子搭載部が適正の間隔を保持
していても他の素子搭載部は電気絶縁を維持でき
ないほどに放熱フインに接近したり、放熱性を害
するほどに間隔が開いたりする。[Technical Background of the Invention] When a lead frame on which a semiconductor chip is mounted is sealed with a resin together with a heat dissipation fin, the distance between the element mounting portion and the heat dissipation fin is adjusted to a desired value so that both electrical insulation and heat dissipation are achieved. It is extremely difficult to control the value and perform transfer molding. especially,
Lead frames equipped with multiple semiconductor chips are large, so they curve during molding, and even if one element mounting part maintains an appropriate distance from the heat dissipation fin, other element mounting parts are exposed to electricity. They may be so close to the heat dissipation fins that insulation cannot be maintained, or they may be so far apart that they impair heat dissipation.
このため比較的大形のリードフレームをもつ半
導体装置では第一及び第二樹脂封止をする二重モ
ールド方式が採用されている。以下第４図によつ
て、従来の二重モールド方式を説明する。 For this reason, semiconductor devices having relatively large lead frames employ a double molding method in which first and second resin sealing is performed. The conventional double mold method will be explained below with reference to FIG.
第４図ａは、パワートランジスタアレーについ
て第一樹脂封止をした成形品の平面図、第４図ｂ
は第４図ａ，ｂ−ｂ線に沿う断面図である。この
アレーは、第４図ａ及び第４図ｂにみるように、
６個の半導体チツプ１がリードフレームの６箇所
の素子搭載部２ａにそれぞれ搭載されており、各
半導体チツプ１はボンデイングワイヤ３によりリ
ードフレームのリード２ｂとの間に回路構成され
ている。半導体チツプ１を搭載したリードフレー
ムは素子搭載部の裏面２ｃが露出するように常法
によりエポキシ樹脂で封止成形されて第一の樹脂
封止部４が形成される。 Figure 4a is a plan view of the molded product with the power transistor array sealed with the first resin, Figure 4b
FIG. 4 is a sectional view taken along line a and bb in FIG. 4. This array, as seen in Figures 4a and 4b,
Six semiconductor chips 1 are respectively mounted on six element mounting portions 2a of a lead frame, and a circuit is formed between each semiconductor chip 1 and a lead 2b of the lead frame by a bonding wire 3. The lead frame on which the semiconductor chip 1 is mounted is sealed and molded with epoxy resin by a conventional method so that the back surface 2c of the element mounting part is exposed to form a first resin sealing part 4.
第４図ｃは第二樹脂封止をした製品の平面図、
第４図ｄは第４図ｃのｄ−ｄ線に沿う断面図であ
る。第一樹脂封止をした成形品Ａは、素子搭載部
の裏面２ｃが放熱フイン５と微小な間隔をおいて
金型内に配置され、第一樹脂封止と同じエポキシ
樹脂で封止成形されて第二の樹脂封止部６が形成
される。第二樹脂封止のエポキシ樹脂は、第一樹
脂封止をした成形品Ａと放熱フイン５両者の外周
６ａと、成形品Ａと放熱フイン５との間隙６ｂに
充填されている。 Figure 4c is a plan view of the product sealed with the second resin;
FIG. 4d is a sectional view taken along line dd in FIG. 4c. In the molded product A that has been sealed with the first resin, the back surface 2c of the element mounting part is placed in the mold with a small distance from the heat dissipation fin 5, and the molded product A is sealed with the same epoxy resin as the first resin seal. A second resin sealing portion 6 is thus formed. The epoxy resin for the second resin sealing is filled in the outer periphery 6a of both the molded product A and the heat radiation fin 5, which have been sealed with the first resin, and the gap 6b between the molded product A and the heat radiation fin 5.
［発明の技術的背景とその問題点］
上記従来の二重モールド方式の樹脂封止におい
ては、第一樹脂封止した成形品Ａの剛性のほうが
リードフレーム単独であるときの剛性よりも大き
いので、素子搭載部の裏面２ｃと放熱フイン５の
間隙６ｂを、すべて所望の値にすることがより容
易となる。従つてその間隙６ｂをできるかぎり薄
くして放熱特性を改善することができる。しかし
ながらその反面、第一樹脂封止部４と第二樹脂封
止部６との界面の密着力が弱く、機械的衝撃を受
けると該界面に亀裂やエアーギヤツプが入りやす
い欠点があり、それが放熱特性を劣化させる原因
となつていた。[Technical background of the invention and its problems] In the conventional double mold resin sealing described above, the rigidity of the first resin-sealed molded product A is greater than the rigidity of the lead frame alone. , it becomes easier to set all the gaps 6b between the back surface 2c of the element mounting portion and the heat dissipating fins 5 to desired values. Therefore, the gap 6b can be made as thin as possible to improve heat dissipation characteristics. However, on the other hand, there is a drawback that the adhesion of the interface between the first resin sealing part 4 and the second resin sealing part 6 is weak, and cracks and air gaps are likely to form at the interface when subjected to mechanical shock, which causes heat dissipation. This caused the characteristics to deteriorate.
［発明の目的］
本発明の目的は、二重モールド方式の樹脂封止
型半導体装置において、第一樹脂封止部と第二樹
脂封止部との密着力を改善し、半導体装置の機械
的衝撃に対する信頼性を高め、安定した放熱特性
を得ようとするものである。[Object of the Invention] An object of the present invention is to improve the adhesion between the first resin sealing part and the second resin sealing part in a double mold type resin-sealing semiconductor device, and to improve the mechanical properties of the semiconductor device. The aim is to improve reliability against shock and obtain stable heat dissipation characteristics.
［発明の概要］
本発明は、二重モールド方式における第一樹脂
封止部に切欠き又は貫通孔を設け、該切欠き又は
貫通孔が第二樹脂封止部に対してアンダーカツト
となるテーパ若しくは段をもつことを特徴として
いる。[Summary of the invention] The present invention provides a taper in which a notch or a through hole is provided in a first resin sealing part in a double molding method, and the notch or through hole is undercut with respect to a second resin sealing part. Or, it is characterized by having steps.
［発明の実施例］
次に図面を参照して本発明の実施例を説明す
る。以下の図面で第４図におけると同じ符号を付
した部分は従来方式における部分と同じであるか
らその説明を省略する。[Embodiments of the Invention] Next, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the parts given the same reference numerals as in FIG. 4 are the same as the parts in the conventional system, and therefore the explanation thereof will be omitted.
第１図Ａは、第一樹脂封止部１４の外周４箇所
に切欠き２０を設けて第一樹脂封止をした成形品
の平面図、第１図Ｂは第１図ＡのＢ−Ｂ線に沿う
一部拡大断面図である。第１図の該切欠き２０
は、特に第二樹脂封止部との結合を完全にするた
め内部リードの一部２ｄが切欠きによつて露出す
る部分に設けられている。かかる第一樹脂封止成
形品を成形するには、たとえば該内部リードの一
部２ｄを支承する突起を有する下型キヤビテイと
該突起に対応するとともにテーパ２１をもつ突起
を設けた上型キヤビテイの成形型を用い、リード
フレームのチツプ搭載部の裏面２ｃが該第一樹脂
封止部において露出するように該裏面２ｃを下型
キヤビテイの表面に密着させるように配置してト
ランスフア成形することによつて得られる。 FIG. 1A is a plan view of a molded product in which notches 20 are provided at four locations on the outer periphery of the first resin sealing portion 14 and the first resin sealing is performed, and FIG. 1B is B-B in FIG. 1A. It is a partially enlarged sectional view along the line. The cutout 20 in FIG.
is provided at a portion where a portion 2d of the internal lead is exposed by the notch, particularly in order to complete the connection with the second resin sealing portion. In order to mold such a first resin-sealed molded product, for example, a lower mold cavity having a protrusion supporting the part 2d of the internal lead and an upper mold cavity having a protrusion corresponding to the protrusion and having a taper 21 are used. Using a mold, transfer molding is performed by placing the back surface 2c of the chip mounting portion of the lead frame in close contact with the surface of the lower mold cavity so that the back surface 2c is exposed at the first resin sealing portion. You can get it by twisting it.
第１図Ｃは、この実施例で第二樹脂封止をした
製品の平面図、第１図Ｄは第１図ＣのＤ−Ｄ線に
沿う一部拡大断面図である。この実施例の第二樹
脂封止ではエポキシ樹脂が、第一樹脂封止部１４
と放熱フイン５両者の外周１６ａと、第一樹脂封
止部１４と放熱フイン５との間隙１６ｂとに充填
されることは従来例と同様であるが、それに加え
て、第一樹脂封止部の切欠き内１６ｃにもエポキ
シ樹脂が充填される。切欠き２０のテーパ２１
は、第二樹脂封止部に対してアンダーカツトの逆
テーパ（好ましくは5゜以上、より好ましくは10゜
以上とする）になつているから、第一樹脂封止部
と第二樹脂封止部の界面２２における密着力が改
善される。 FIG. 1C is a plan view of a product sealed with a second resin in this embodiment, and FIG. 1D is a partially enlarged cross-sectional view taken along line DD in FIG. 1C. In the second resin sealing of this embodiment, the epoxy resin is used in the first resin sealing part 14.
The outer periphery 16a of both the first resin sealing part 14 and the heat dissipating fin 5 and the gap 16b between the first resin sealing part 14 and the heat dissipating fin 5 are filled as in the conventional example, but in addition, the first resin sealing part The inside of the notch 16c is also filled with epoxy resin. Taper 21 of notch 20
The undercut has a reverse taper (preferably 5 degrees or more, more preferably 10 degrees or more) with respect to the second resin sealing part, so the first resin sealing part and the second resin sealing part The adhesion force at the interface 22 of the part is improved.
第２図は本発明で採用できる別の切欠き又は貫
通孔の形状を示したものである。本発明において
は、上記実施例第１図Ｄや第２図Ａにみるような
第一樹脂封止部の外周における切欠き２０，２０
ａに限らず、第２図Ｂ又は同図Ｃにみるような第
一樹脂封止部の内部における貫通孔２３ａ，２３
ｂであつてもよい。また、切欠き又は貫通孔は、
上記実施例第１図Ｄや第２図Ａ，Ｂにみるような
第二樹脂封止部に対してアンダーカツトのテーパ
を有するものに限らず、第２図Ｃにみるような第
二樹脂封止部に対してアンダーカツトとなる段を
有するものであつてもよいのは当然である。 FIG. 2 shows another shape of the cutout or through hole that can be employed in the present invention. In the present invention, notches 20, 20 on the outer periphery of the first resin sealing part as shown in FIG. 1D and FIG. 2A of the above embodiments are used.
Not limited to the through holes 23a and 23 inside the first resin sealing part as shown in FIG. 2B or C.
It may be b. In addition, the notch or through hole is
The second resin sealing part is not limited to the one having an undercut taper with respect to the second resin sealing part as shown in FIG. 1D and FIGS. It goes without saying that it may have a step that undercuts the stop.
［発明の効果］
本発明の二重モールド形式の樹脂封止型半導体
装置によれば、第一樹脂封止部と第二樹脂封止部
との密着力が改善されるから、半導体装置の機械
的衝撃に対する信頼性が高まり、両樹脂封止部の
界面に亀裂やエアーギヤツプが入らないので放熱
特性が安定するという効果が得られる。[Effects of the Invention] According to the double-molded resin-sealed semiconductor device of the present invention, the adhesion between the first resin-sealed part and the second resin-sealed part is improved, so that the semiconductor device machine can be improved. The reliability against physical impact is increased, and since there are no cracks or air gaps at the interface between the two resin-sealed parts, the heat dissipation characteristics are stabilized.
その効果を具体的に説明すれば、厚さ２mmの放
熱フインをもち外形寸法が75×75×６（厚さ）mm
である第１図実施例の半導体装置を相当数試料と
し、まず、第１図Ｃの半導体素子の所定位置Ｅ１
〜Ｅ６それぞれにおける熱抵抗Rthの分布を測定
し、次に機械的衝撃として75cmの高さから厚さ３
mmの鉄板上に５回落下させる落下試験を実施した
後の熱抵抗の分布を求めた。一方、従来の二重モ
ールド形式の従来装置についても、同様の試験を
行ない、第３図のとおり結果が得られた。第３図
に明らかなように、本発明の半導体装置では落下
試験後の熱抵抗値が初期値とほとんど変らず、機
械的衝撃に対して極めて安定している。 To explain the effect specifically, it has heat dissipation fins with a thickness of 2 mm and external dimensions of 75 x 75 x 6 (thickness) mm.
Using a considerable number of samples of the semiconductor device of the embodiment shown in FIG.
~ Measure the distribution of thermal resistance R th in each of E6, and then apply a mechanical shock from a height of 75 cm to a thickness of 3
The distribution of thermal resistance was determined after conducting a drop test in which the sample was dropped 5 times onto a steel plate of mm. On the other hand, similar tests were conducted on a conventional device of the conventional double mold type, and the results shown in FIG. 3 were obtained. As is clear from FIG. 3, in the semiconductor device of the present invention, the thermal resistance value after the drop test is almost unchanged from the initial value, and is extremely stable against mechanical shock.
第１図は本発明の二重モールド形式の半導体装
置を説明する図で、同図Ａは第一樹脂封止をした
成形品の平面図、同図Ｂは同図ＡのＢ−Ｂ線に沿
う一部拡大断面図、同図Ｃは第二樹脂封止をした
製品の平面図、同図Ｄは同図ＣのＤ−Ｄ線に沿う
一部拡大断面図、第２図ＡないしＣは他の実施例
の第一樹脂封止部の部分斜視図、第３図は本発明
の効果を説明するグラフ、第４図ａないしｄは従
来の二重モールド形式の半導体装置を第１図と同
様に説明する図である。
１……半導体素子、２ｃ……素子搭載部裏面、
４，１４……第一樹脂封止部、５……放熱フイ
ン、６，１６……第二樹脂封止部、２０，２０ａ
……切欠き、２３ａ，２３ｂ……貫通孔。
FIG. 1 is a diagram illustrating a double mold type semiconductor device of the present invention, where A is a plan view of a molded product sealed with the first resin, and B is a diagram taken along the line B-B in FIG. Figure C is a plan view of the product sealed with the second resin; Figure D is a partially enlarged cross-sectional view taken along line D-D in Figure C; Figures 2 A to C are FIG. 3 is a graph explaining the effects of the present invention, and FIGS. 4 a to 4 d show a conventional double-molded semiconductor device similar to that shown in FIG. 1. It is a figure explaining similarly. 1... Semiconductor element, 2c... Back side of element mounting part,
4, 14...First resin sealing part, 5...Radiating fin, 6,16...Second resin sealing part, 20, 20a
...notch, 23a, 23b...through hole.
Claims (1)
とともに、金属細線で該半導体素子を接続するこ
とにより回路構成をしたリードフレームと、該リ
ードフレームの素子搭載部の裏面が露出するよう
に封止成形した第一樹脂封止部と、該第一樹脂封
止部に露出した素子搭載部裏面に対向して間隙を
保つように放熱フインを設置するとともに、該放
熱フインの非対向面が露出するように該第一樹脂
封止部と放熱フインとを封止成形した第二樹脂封
止部とを有する半導体装置において、該第一樹脂
封止部に切欠き又は貫通孔を設け、該切欠き又は
貫通孔が該第二樹脂封止部に対してアンダーカツ
トとなるテーパ若しくは段をもつことを特徴とす
る樹脂封止型半導体装置。 ２ 切欠きを、第一樹脂封止部の外周部分に設け
た特許請求の範囲第１項記載の樹脂封止型半導体
装置。[Claims] 1. A lead frame on which at least one semiconductor element is mounted and a circuit is configured by connecting the semiconductor elements with thin metal wires, and the back side of the element mounting portion of the lead frame is exposed. A heat dissipation fin is installed so as to maintain a gap between the first resin sealing part molded as shown in FIG. In a semiconductor device having the first resin sealing part and a second resin sealing part formed by sealing and molding the heat dissipation fin so that the surface is exposed, a notch or a through hole is provided in the first resin sealing part. . A resin-sealed semiconductor device, wherein the notch or through-hole has a taper or step that undercuts the second resin-sealed portion. 2. The resin-sealed semiconductor device according to claim 1, wherein the notch is provided in the outer peripheral portion of the first resin-sealed portion.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60214852A JPS6276659A (en) | 1985-09-30 | 1985-09-30 | Resin sealed type semiconductor device |
| EP86304725A EP0206771B1 (en) | 1985-06-20 | 1986-06-19 | Packaged semiconductor device |
| DE8686304725T DE3684184D1 (en) | 1985-06-20 | 1986-06-19 | ENCLOSED SEMICONDUCTOR ARRANGEMENT. |
| KR1019860006270A KR900001668B1 (en) | 1985-09-30 | 1986-07-30 | Resin Sealed Semiconductor Device |
| US07/334,771 US4924351A (en) | 1985-06-20 | 1989-04-10 | Recessed thermally conductive packaged semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60214852A JPS6276659A (en) | 1985-09-30 | 1985-09-30 | Resin sealed type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6276659A JPS6276659A (en) | 1987-04-08 |
| JPH0357623B2 true JPH0357623B2 (en) | 1991-09-02 |
Family
ID=16662612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60214852A Granted JPS6276659A (en) | 1985-06-20 | 1985-09-30 | Resin sealed type semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS6276659A (en) |
| KR (1) | KR900001668B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3035403B2 (en) * | 1992-03-09 | 2000-04-24 | 富士通株式会社 | Semiconductor device |
-
1985
- 1985-09-30 JP JP60214852A patent/JPS6276659A/en active Granted
-
1986
- 1986-07-30 KR KR1019860006270A patent/KR900001668B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| KR900001668B1 (en) | 1990-03-17 |
| KR870003559A (en) | 1987-04-18 |
| JPS6276659A (en) | 1987-04-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |