JPH0357714B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switching regulator used in a stabilized DC power supply.

[Conventional technology and its problems]

A DC- DC converters are already known. By the way, a typical conventional on-on type DC-DC converter (FCC) is
It uses an oscillator to create a pulse width modulated wave (PWM wave), and is configured as a separately excited type that controls the conversion switching transistor on and off. Therefore, the circuit has become complex and expensive.

As a DC-DC converter with a simple circuit configuration,
There is an on-off type self-excited DC-DC converter (RCC), but it has the disadvantage that the oscillation frequency increases under light loads, increasing the number of switching operations and increasing switching loss. Another disadvantage is that it is difficult to use field effect transistors as switching elements.

In order to solve the above-mentioned problems, the applicant has filed Japanese Patent Applications No. 61-6666, No. 61-6667, No. 61-6667, No. 61-6667, No.
61-6669 proposed a new method in which the turning-on point of a conversion switch is determined by the charging voltage of a capacitor. According to this method, the voltage conversion switch is turned on and off by periodic charging and discharging of the capacitor.
The circuit configuration is simplified because of the off-control. However, this document does not disclose a specific technique for significantly reducing power loss when the power supply voltage is high.

Therefore, an object of the present invention is to reduce power loss particularly when the power supply voltage is high in a switching regulator that periodically charges and discharges a capacitor to determine when a conversion switch is turned on. .

[Means for solving problems]

To achieve the above-mentioned objects, the present invention turns on and off the voltage supplied from a DC power supply, and is configured to turn on when the voltage at the control terminal reaches a threshold voltage. For example, a voltage adjustment switch such as FET 5, a voltage conversion winding for obtaining an output voltage corresponding to on/off of the voltage adjustment switch, and a voltage conversion winding are electromagnetically coupled to the voltage conversion winding, and the switch is A transformer having a switch driving winding, such as the tertiary winding 14, connected to the control terminal for on-driving, a rectifying and smoothing circuit connected to the output side of the converting winding, Therefore, a first capacitor is connected in series to the switch drive winding so as to turn on the switch, and a charging resistor is connected between the DC power source and the first capacitor. a second charging circuit connected to both ends of the first capacitor and charging the first capacitor based on a voltage lower than the voltage of the DC power supply obtained via the transformer; , a second capacitor for determining when the voltage adjustment switch starts to turn off, and a third charging circuit that starts charging the second capacitor in response to a time when the voltage adjustment switch starts to turn on. , in response to the second capacitor being charged to a predetermined value, the on-drive of the voltage regulating switch by the voltage of the drive winding is cut off to turn the voltage regulating switch into an off state; The present invention relates to a switching regulator comprising the voltage regulating switch and a control circuit connected to the first and second capacitors so as to place the first and second capacitors in a discharge state.

In addition, to explain the correspondence between the present invention and the embodiments, the first charging circuit is a resistor 16, and the second charging circuit is, for example, a winding 41 and a diode 4.
2, capacitor 44, resistor 45, and diode 46
The third charging circuit is a circuit consisting of a second charging circuit.
The control circuit is a circuit including a control transistor 19. The control circuit is a circuit including a control transistor 19.

[Function] According to the present invention, the first capacitor is not charged only by the first charging circuit connected to the DC power source, but also charged by the second charging circuit connected to the transformer. This makes it possible to reduce the current flowing through the resistor of the first charging circuit, thereby reducing power loss there. Note that since the second charging circuit charges the first capacitor by obtaining a voltage lower than the voltage of the DC power source from the transformer, the power loss does not become so large even if the charging current required by the first capacitor flows.

[First Embodiment] Next, referring to FIGS. 1 and 2, the first embodiment of the present invention will be described.
A DC-DC converter according to an embodiment will be explained.
In FIG. 1, one end of a primary winding 3 of a transformer 2 is connected to one DC power supply terminal 1. 1
Between the other end of the next winding 3 and the other DC power supply terminal 4, an N-channel insulated gate type (MOS type) field effect transistor or FET is connected as a conversion switch.
5 is connected. FET5 has a drain as the first terminal, a source as the second terminal, and a gate as the control terminal, and when the gate voltage reaches the threshold voltage V _TH , the drain and source become conductive (on state). It is something.

The transformer 2 has a primary winding 3 and a secondary winding 6 as voltage conversion windings or main windings, and also has a tertiary winding 14 as a switch drive winding, and further has a capacitor charging winding. It has a quaternary winding 41 of.

The secondary winding 6 electromagnetically coupled to the primary winding 3 has
A rectifying and smoothing circuit 11 consisting of two diodes 7 and 8, a reactor 9, and a capacitor 10 is connected. Output terminals 12 and 13 connected to the rectifying and smoothing circuit 11 are parts that supply a stabilized output voltage to a load. The output circuit according to the invention comprises:
It is composed of a transformer 2 and a rectifying and smoothing circuit 11.

One end of the tertiary winding 14, which is electromagnetically coupled to the primary winding 3 and the secondary winding 6, is connected to a first capacitor 15.
is connected to the gate of FET 5 through the terminal, and the other end is connected to the source. A resistor 16 is connected between one power supply terminal 1 and the gate as a first charging circuit. This resistor 16 determines the charging time constant of the first capacitor 15.

The second charging circuit according to the present invention for charging the first capacitor 15 includes a quaternary winding 41, a charging power supply capacitor 44 connected in parallel to the quaternary winding 41 via a diode 42 and a resistor 43, It consists of a resistor 45 and a diode 46 connected between this power supply capacitor 44 and the first capacitor 15.

A second capacitor 17 is provided to determine when the FET 5 is turned off. The charging circuit for this second capacitor 17 connects this capacitor 17 to the tertiary winding 1 through a resistor 18 that determines the charging time constant.
4 are connected in parallel.

A control circuit for periodically charging and discharging the first and second capacitors 15 and 17 and determining the off point of the FET 5 in response to the voltage of the second capacitor 17 connects the gate and source of the FET 5. It has a control transistor 19 connected therebetween via a reverse current blocking diode _D1 . A second transistor is connected between the base and emitter of this control transistor 19.
A capacitor 17 is connected. The control transistor 19 starts conducting when a voltage of a predetermined value (for example, about 0.6 V) or more is applied between the base and emitter, and substantially short-circuits the gate and source of the FET 5. The diode D ₂ connected in parallel to the second capacitor 17 is for keeping the reverse charging voltage of the second capacitor 17 constant.

The constant voltage control circuit includes voltage detection resistors 20 and 21 connected between output terminals 12 and 13, one input terminal connected to a voltage dividing point of these resistors 20 and 21, and the other input terminal connected to a reference voltage. It consists of an error amplifier 23 connected to a source 22, a light emitting diode 24 connected to the output terminal of the error amplifier 23, and a phototransistor 25 optically coupled to the light emitting diode 24. The phototransistor 25 is provided as a variable impedance element for changing the charging time constant of the second capacitor 15, and is connected in parallel to the resistor 18. Charging of the second capacitor 17 therefore takes place through the resistor 18 and the phototransistor 25.

In order to reset the residual magnetism of the transformer 2 by the flyback voltage, a resistor 27 is connected in parallel to the primary winding 3 via a diode 26. Further, a capacitor 28 is connected in parallel to the resistor 27 in order to suppress flyback voltage.

(Operation) When DC voltage is supplied from the pair of power supply terminals 1 and 4, the first capacitor 15 is
charging starts. The first capacitor 15 is charged according to the charging time constant R ₁ C ₁ determined by the capacitance C ₁ and the value R ₁ of the resistor 16, and the voltage source V _C1 across the first capacitor 15 is t shown in FIG. It gradually increases as shown in ₁ to _t4 . Since FET 5 has a threshold voltage V _TH (rise voltage), it does not turn on immediately when the power is turned on, but when the first capacitor 15 is charged to the threshold voltage V _TH or higher.
Turns on at t ₃ . When FET5 is turned on, the voltage between the drain and source of FET5 is as shown in Figure 2C.
Since V _DS becomes low and the power supply voltage is applied to the primary winding 3, the tertiary winding 1 is lowered as shown in FIG. 2D.
A voltage V ₃ is generated in the tertiary winding 14, and the voltage of this tertiary winding 14 is
V ₃ becomes a positive feedback voltage and is applied to the gate of FET5. Since the voltage of the power supply terminal 1 is set higher than the voltage V ₃ of the tertiary winding 14, it is charged even during the period t ₃ to t ₄ when the FET 5 is on, and the capacitor voltage
The gate voltage is the sum of V _C1 and the tertiary winding voltage V ₃
It becomes V _G. Note that a current flows through the source-gate capacitance of the FET 5 based on the positive voltage obtained in the tertiary winding 14. As a result, the tertiary winding 14
The positive voltage of allows the capacitor 15 to discharge,
Thereafter, the capacitor 15 is charged to the opposite polarity. When the FET 5 is turned on, a drain current _ID flows as shown in FIG. 2B, and a voltage that turns on the diode 7 is generated in the secondary winding 6 of the transformer, which is smoothed and becomes the output voltage.

From the time t ₃ when FET 5 turns on and a positive voltage is generated across the tertiary winding 14, the second capacitor 1
7 starts charging in the positive direction, and this charging voltage V _C2 gradually increases as shown in FIG. 2F. When the capacitor voltage V _C2 exceeds the rising voltage (approximately 0.6 V) of the control transistor 19, the transistor 19 is turned on, the gate and source are substantially short-circuited, and the gate voltage V _G reaches the threshold. The voltage becomes lower than that, and FET5 turns off.
When the transistor 19 is turned on, the first capacitor 1
5 charges are applied to diode D ₁ , transistor 19,
It is released in the circuit of the tertiary winding 14, and a voltage above the threshold is generated through the first capacitor 15.
It becomes impossible to feed to FET5.

During the ON period of FET 5 after startup, the 4th winding 4
1, a voltage corresponding to the voltage of the primary winding 3 is obtained,
As a result, the charging power supply capacitor 44 is charged. Now, if the charging current required by the first capacitor 15 is 10 mA, this 10 mA is not supplied entirely through the resistor 16, but is supplied from the charging power supply capacitor 44. For example, based on the power supply voltage of DC300V, only 0.5mA flows through the resistor 16, and 10-0.5=9.5mA is the charge power supply capacitor 4.
Start from 4. In order to significantly reduce power loss, the charging voltage of the charging power supply capacitor 44 is set to, for example, 10V, which is significantly lower than DC 300V. As a result, in the absence of the charging power supply capacitor 44 according to the present invention, the resistor 16
(V) × 10 (mA) = 3W power loss occurred, whereas in the circuit of FIG.
Power loss due to resistor 45 is 10 (V) x 9.5 (mA) =
0.095W, resulting in a total power loss of only 0.245W, which is approximately less than the case with only 16 resistors.
92% less power loss.

When FET 5 is turned off at _t1 in FIG. 2, a flyback voltage _VF is generated and the direction of the tertiary winding voltage _V3 is reversed as shown in FIG. 2D. The reverse voltage in the tertiary winding 14 generated between t ₁ and _{t 2} charges the second capacitor 17 in the reverse direction. Since the diode D ₂ is connected in parallel to the second capacitor 17, the reverse charging voltage can be suppressed to a constant value. At this time, the control transistor 19 is reverse biased and in an off state. The voltage of the tertiary winding 14 during the off period charges the first capacitor 15 through the source-gate capacitance of the FET 5. Therefore, during the period t ₁ to _{t 2} in which the flyback voltage is generated, the voltage of the tertiary winding 14, the power supply voltage, and the capacitor 44 are
The first capacitor 15 is charged with a voltage based on . The reverse voltage of the tertiary winding 14 based on the flyback voltage is determined by the fact that the ON time width T _ON of the FET 5 is wide.
The larger the drain current I _D is, the higher it becomes. Therefore,
As the on-time width T _ON of the FET 5 becomes wider, the slope of the rise in the charging voltage of the first capacitor 15 becomes larger, and as a result, the on-time width T _OFF of the FET 5 becomes narrower.
Therefore, even if the load current fluctuates, the on/off period of the FET 5 does not change much and remains almost constant.

Since the gate voltage V _G is the sum of the capacitor voltage V _C1 and the tertiary winding voltage V ₃ , it changes as shown in FIG. 2A, and during the period t ₁ to _{t 2} during which the flyback voltage V _F is generated. In this case, the voltage V _C1 −V _F becomes the gate voltage V _G. When the reset of transformer 2 is completed at t ₂ , the flyback voltage V _F also disappears, so
Capacitor voltage V _C1 becomes gate voltage V _G. 1st
The charging of capacitor 15 further progresses, and at t ₃ FET 5
When the threshold voltage V _TH of FET5 is reached, FET5
is turned on. The on-time width T _ON from t ₃ to _{t 4} after turning on is R, which is composed of the combined resistance value R ₂ of the resistor 18 and the phototransistor 25 and the value C ₂ of the second capacitor 17, as at the time of startup. ₂ C Determined by ₂ time constant circuit.

The output voltage is controlled by controlling the resistance value of the phototransistor 25. Now, if the output voltage becomes lower than a certain value, the output of the error amplifier 23 becomes low, the amount of light from the light emitting diode 24 decreases, and the resistance value of the phototransistor 25 increases.
Therefore, the charging current supplied by the charging circuit consisting of the resistor 18 and the phototransistor 25 decreases, and the charging speed of the second capacitor 17 becomes slower as shown by the dotted line in FIG. The time it takes for the voltage to reach the rising voltage of transistor 19 becomes longer. As a result, the on-time width T _ON from t ₃ to _{t 4} becomes longer, and the output voltage is returned to a predetermined value by increasing the duty ratio. When the output voltage becomes higher than the reference value, the operation is opposite to the above.

When a short circuit occurs between the output terminals 12 and 13, the voltage of each winding of the transformer 2 decreases, and eventually the voltage of the charging power supply capacitor 44 also decreases, and the charging current of the first capacitor 15 decreases, causing the first The voltage of the capacitor 15 hardly reaches the level that turns on the FET 5, the duty ratio decreases, and the load current can be suppressed.

[Second Embodiment] Next, a second embodiment of the present invention shown in FIGS. 3 and 4 will be described. However, in the second and subsequent embodiments and modifications, parts common to those in FIGS. 1 and 2 are given the same reference numerals, and their explanations will be omitted. In this embodiment, a transistor 30 is connected in parallel to the first capacitor 15 via a diode D ₃ , and the base of the transistor 30 is connected via a resistor 31 to the lower end of the tertiary winding 14 . Therefore _, if a flyback voltage is generated in the period t ₁ to _{t 2} in FIG. 4 and a reverse voltage is generated in the tertiary winding 14 as shown in FIG. is turned on, charging of the first capacitor 15 is prohibited, and charging of the first capacitor 15 starts from time _t2 after the transformer 2 is reset, as shown in FIG. 4E. This completely prevents the gate voltage V _G from reaching the threshold voltage V _TH before the transformer 2 is reset. Further, when the reset of the transformer 2 is completed, vibration (not shown) occurs in the primary winding 3 of the transformer 2, but since the first capacitor 15 is in an uncharged state, the positive feedback voltage due to the vibration and the capacitor voltage V _C1
There is no risk that the sum of V TH and FET 5 will not reach the threshold voltage V _TH of FET 5, and FET 5 will be turned on by mistake.

At time _t2 , the transistor 30 is turned off, so charging of the first capacitor 15 starts from this time, and at time _t3 , the FET 5 is turned on.

32 is an overcurrent detection resistor, which is connected in series to the source of FET5. transistor 19
The emitter of is not directly connected to the source but is connected to the resistor 3.
It is connected to the left end of 2. Therefore, the voltage V _C2 of the second capacitor 17 and the voltage V _O across the resistor 32
is applied between the base and emitter of transistor 19. Therefore, when an overcurrent flows, the transistor 19 is turned on while the charging voltage V _C2 of the second capacitor 17 is low, and the FET 5
is turned off, and the on period t ₃ to t ₄ of the FET 5 is shortened.

[Third Embodiment] Next, a DC-DC converter according to a third embodiment of the present invention shown in FIG. 5 will be described. In Figure 5,
To bias the phototransistor 25, a diode 33 and a capacitor 34 are connected in parallel to the winding 14, and the collector of the phototransistor 25 is connected to the capacitor 34. Further, a resistor 35 is connected in parallel to the second capacitor 17. In this circuit, charging current flows into the second capacitor 17 from both the resistor 18 and the phototransistor 25. Note that the polarity of the secondary winding 6 in FIG. 5 is opposite to that in FIG. 1. Therefore, the diode 7 is in a reverse bias state during the ON period of the FET 5, and no energy is output from the secondary winding 6.
When the FET 5 is turned off, an upward voltage is generated in the secondary winding 6 by the magnetic reset operation of the transformer 2, and the energy of the transformer 2 is released via the diode 7, smoothed by the capacitor 10, and output. be done.

[Fourth Embodiment] FIG. 6 shows a DC-DC converter of the fourth embodiment, and FIG. 7 shows the states of each part in FIG. 6. In this embodiment, voltage control is performed by controlling the charging current of the first capacitor 15. That is,
Resistors 16a and 16b are connected between the DC power supply terminal 1 and the first capacitor 15, and the resistor 16b and the first
phototransistor 2 for capacitor 15 of
5 are connected in parallel. When the output voltage changes in this circuit, the current bypassed to the phototransistor 25 changes, the charging current of the first capacitor 15 changes according to the change in the resistance value of the phototransistor 25, and the first capacitor 15 becomes the threshold voltage. The time it takes to reach the hold voltage V _TH changes as shown by the solid line and dotted line in FIG. 7E, and the point at which the FET 5 starts to turn on also changes.

[Fifth Embodiment] In a fifth embodiment shown in FIG. 8, a phototransistor 25 is connected in parallel to the resistor 16. Therefore, the first capacitor 15 is charged by the current flowing through the resistor 16, the phototransistor 25, and the resistor 45. In this embodiment, the first capacitor 15
is moved below the tertiary winding 14 and connected to the gate via the tertiary winding 14 and the diode _D1 .
Also, in order to charge the second capacitor 17,
A fifth winding 14a is provided independently, to which a capacitor 17 is connected via a diode _D2 and a resistor 18.

[Sixth Embodiment] Since the capacitor 50 of the sixth embodiment shown in FIG. 9 has a small capacity, the capacitor 17 of FIG.
It has an essentially different function and is provided solely for bias voltage stabilization. On the other hand, resistance 3
Since the value of 2 is relatively large, the control transistor 19 is turned on largely depending on the detection voltage V _O based on this resistor 32. A capacitor 51 is provided as a bias power supply and is connected to the tertiary winding 14 via a diode 52. capacitor 5
The voltage of 1 is divided by the phototransistor 25 and the resistor 53 and supplied to the base of the transistor 19.

(Operation) When DC voltage is supplied from the pair of power supply terminals 1 and 4, charging of the capacitor 15 is started by the circuit consisting of the resistor 16, the capacitor 15, and the tertiary winding 14. The capacitor 15 is charged according to a time constant R ₁ C ₁ due to the capacitance C ₁ and the value R ₁ of the resistor 16, and the voltage V _C1 across the capacitor 15 gradually increases. FET5
has a threshold voltage V _TH (rise voltage), so it does not turn on immediately when the power is turned on, and the capacitor 15 has a threshold voltage V TH (rising voltage).
Turns on when charged above V _TH . When FET5 is turned on, an output voltage is obtained using the same principle as in the case of FIG.

A flyback voltage is generated during the off period of the FET 5, and the drain-source voltage _VDS becomes high as shown in FIG. 2C. Further, as shown in FIG. 2D, a voltage in the opposite direction is generated in the tertiary winding 14 during the period from _t1 to _t2 until the residual magnetism of the transformer 2 is reset.

Next, the ON end control of the FET 5 shown in FIG. 9 will be explained. Diode 52 and capacitor 5 in Figure 9
1. The phototransistor 25, the resistor 53, and the capacitor 50 function as a variable bias circuit.
A DC bias voltage V _B is supplied as shown in Figure 1C. Base-emitter voltage of transistor 19
V _BE is the sum of the voltage V _A of the power supply detection resistor Ri and the bias voltage V _B. If the rising voltage (threshold voltage) of transistor 19 is 0.6V, transistor 19 is turned on when V _A +V _B reaches 0.6V. Since the bias voltage V _B is a smooth voltage, it does not change over a short period of time, but the current detection voltage V _A changes depending on the drain current shown in Figure 11A.
Changes depending on _ID . And the drain current I _D
increases with time due to flowing through the transformer primary winding 3. The constants of each part are determined so that the transistor 19 does not turn on at the voltage that is the sum of the current detection voltage V _A and the bias voltage V _B at the time when the FET 5 starts to turn on. As shown in FIG. 11B, when the current detection voltage V _A gradually increases,
Base-emitter voltage V _BE of transistor 19
gradually increases, and finally the rising voltage (0.6V)
The transistor 19 is turned on. As a result, the gate and source are short-circuited by the transistor 19 and the resistor Ri, the gate voltage V _G drops below the threshold voltage V _TH , and the FET 5 is turned off. While the transistor 19 is kept on during the storage time, the charge in the capacitor 15 is discharged through the circuit including the diode D ₁ , the transistor 19, the resistor Ri, and the tertiary winding 14. When the FET 5 is turned off, a flyback voltage is generated, and a reverse voltage is generated in the tertiary winding 14, and the voltage of the capacitor 15 decreases, so that the FET 5 is maintained off. In this example,
The capacitor 15 is charged again from the time when the FET 5 is turned off, and the FET 5 is turned on again after a certain period of time.

The point in time when FET 5 turns from on to off changes depending on the current detection voltage V _A and the bias voltage V _B. In the period t ₁ to _{t 2} in Fig. 11, when the input voltage (power supply voltage) is small, in the period t ₂ to _{t 3} , when the input voltage is large, and in the period t ₃ to _{t 4} , the drain current (load current ) is large, the period from t ₄ to _{t 5} shows the waveforms of each part when the drain current is small. If the input voltage between t ₁ and _{t 2} is small, the drain current _ID and current detection voltage V _A at the time of turning on will also be small, so as shown in Fig. 11 D
As shown in , it takes a relatively long time for V _BE to reach 0.6V, resulting in a long on time.

When the input voltage between t ₂ and _{t 3} is high, the current detection voltage V _A at the time of turning on becomes high, so the time until V _BE reaches 0.6V becomes short.

When the drain current I _D from t ₃ to _{t 4} is large, the output voltage tends to decrease due to a large voltage drop, the error output and the light amount of the light emitting diode 24 decrease, and the resistance value of the phototransistor 25 decreases. As a result, the bias voltage V _B obtained from the voltage dividing circuit of the phototransistor 25 and the resistor 53 becomes low. Therefore, even if the drain current I _D is large, it takes a long time for V _BE of the transistor 19 to reach 0.6V, and the necessary on-time width can be obtained.

When the drain current between t ₄ and _{t 5} is small, the output voltage tends to increase, the error output and the amount of light from the light emitting diode 24 increase, the resistance value of the phototransistor 25 decreases, and the bias voltage V _B becomes high as shown in FIG. 11C. Therefore, even if the amplitude of the drain current I _D is small, V _BE reaches 0.6 V relatively quickly as shown in FIG. 11D.

As is clear from the above, this circuit is not a self-excited DC-DC converter that utilizes the saturation of a switching transistor, so the on-time T _ON shown in FIG.
The on/off period, which is the sum of T and off time T _OFF , does not change much even if the load fluctuates. Therefore, an increase in the number of switching operations during light loads is suppressed, and switching loss is reduced. Furthermore, even though it is an on-on type, self-sustained oscillation is possible. Further, the circuit configuration can be simplified and miniaturized.

[Modified example]

The present invention is not limited to the embodiments described above, and the following modifications are possible, for example.

(1) As shown in Figure 12, a single-turn transformer type winding 3a is provided in place of the primary and secondary windings 3, 6 of the transformer 2 in Figure 1, and a rectifier and smoothing circuit 11 is connected to this tap. It is also applicable to those who This example is an on-off type in which diode 7 is on when FET 5 is off, so rectifier and smoothing circuit 11 connects diode 7 and capacitor 10.
1, and the polarity of the winding 3a is opposite to that in FIG.

(2) As shown in FIG. 13, it is also applicable to a transformer 2 in which the rectifying and smoothing circuit 11 is directly connected to the primary winding 3 without providing a secondary winding. This is also configured as an on/off type.

(3) As shown in Figure 14, connect the primary winding 3 to the FET5
It may be connected to the drain side of the

(4) As shown in FIG. 15, instead of providing a quaternary winding, the capacitor 44 may be charged with the voltage between the output terminals 12 and 13.

(5) As shown in Figure 16, FET as a switch
5 may be replaced by an optical switch 5a consisting of a light emitting diode 5c and a phototransistor 5b. In this case, the phototransistor 5b is
Connected in series to the next winding 3, a light emitting diode 5c
is connected to the first capacitor 15 via a resistor 70. Therefore, the anode of the light emitting diode 5c functions as a control terminal, and the anode of the light emitting diode 5c functions as a control terminal.
It emits light when the first capacitor 15 is charged above the rising voltage (threshold) of c.
Phototransistor 5b is turned on. Note that a resistor 71 and a diode 7 are connected in parallel to the capacitor 15.
2 is connected, so the tertiary winding 1 when on
A current is supplied to the light emitting diode 5c by the voltage of 4.

(6) As shown in Figure 17, FET as a switch
A transistor 5d may be connected instead of 5. In this case as well, a resistor 71 and a diode 72 are connected in parallel to the first capacitor 15 in order to supply a base current when turned on.

(7) As shown in Fig. 18, the first capacitor 15
may be connected in parallel to the tertiary winding 14. In this case, a resistor 73 is connected in series to the tertiary winding 14.

(8) As shown in Fig. 19, a primary winding 3 is connected in series between the power supply terminal 1 and the output terminal 12, and this primary winding 3 is used as an inductance.
It can be applied to a device in which energy is stored in the primary winding 3 while the FET 5 is on, and is released via the diode 7 when the FET 5 is off.

(9) Instead of the control transistor 19, another control element such as a FET may be used.

〔Effect of the invention〕

As is clear from the above, in the present invention, the capacitor is charged not only based on the power supply voltage but also based on the voltage obtained through the transformer. If the charging voltage is set low enough to match the charging voltage, power loss will be reduced.

[Brief explanation of drawings]

FIG. 1 shows a direct current according to the first embodiment of the present invention.
A block diagram showing the DC converter, Fig. 2 is a waveform diagram of each part of Fig. 1, Fig. 3 is a circuit diagram showing the DC-DC converter of the second embodiment, and Fig. 4 is a diagram of each part of Fig. 3. 5 is a circuit diagram showing the DC-DC converter of the third embodiment, and FIG. 6 is a waveform diagram of the DC-DC converter of the fourth embodiment.
A circuit diagram showing the DC converter, FIG. 7 is a waveform diagram of each part of FIG. 6, FIG. 8 is a circuit diagram showing the DC-DC converter of the fifth embodiment, and FIG. 9 is a circuit diagram of the sixth embodiment. 10 is a waveform diagram of each part of FIG. 9, FIG. 11 is a waveform diagram of the circuit of FIG. 9 when input voltage changes and current changes, FIG. 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17
18 and 19 are circuit diagrams showing modified examples. 1, 4...Power terminal, 2...Transformer, 3...
Primary winding, 5...FET, 6...Secondary winding, 11
... Rectifier smoothing circuit, 12, 13 ... Output terminal, 1
4... Tertiary winding, 15... First capacitor, 4
1... Quaternary winding, 44... Capacitor for charging power supply.

Claims (1)

[Claims] 1. A voltage adjustment switch that turns on and off the voltage supplied from a DC power source and is configured to turn on when the voltage at a control terminal reaches a threshold voltage. , a voltage conversion winding for obtaining an output voltage corresponding to on/off of the switch, and a switch drive that is electromagnetically coupled to the voltage conversion winding and connected to the control terminal to turn on the switch. a transformer having a winding; a rectifying and smoothing circuit connected to the output side of the voltage converting winding; and a rectifying and smoothing circuit connected in series to the switch drive winding so as to turn on the switch by the charging voltage. a first capacitor; a first charging circuit including a charging resistor connected between the DC power supply and the first capacitor; and a first charging circuit connected to both ends of the first capacitor and connected via the transformer. a second charging circuit that charges the first capacitor based on a voltage lower than the obtained voltage of the DC power source; a second capacitor that determines when the voltage adjustment switch starts to turn off; a third capacitor that starts charging the second capacitor in response to the point in time when the voltage adjustment switch starts to turn on;
a charging circuit, and in response to the second capacitor being charged to a predetermined value, the on-drive of the voltage regulating switch by the voltage of the drive winding is cut off, and the voltage regulating switch is turned off. the voltage regulating switch and the first and second capacitors so as to cause the first and second capacitors to discharge.
A switching regulator consisting of a control circuit connected to a capacitor.