JPH0358533B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the method for manufacturing semiconductor devices such as shot-gate field effect transistors using compound semiconductors, we have developed shot-gate gates that can withstand heat treatment of 850°C (°C) or higher. The purpose of this process is to form a shot gate electrode made of silicide containing tungsten on a compound semiconductor, and then ion-implant impurities using the shot gate electrode as a mask. a step of forming a source region and a drain region on both sides of the shot gate electrode, then a step of performing high-temperature heat treatment to activate the implanted impurities;
forming an electrode of a predetermined material on the source region and drain region, and the impurity concentration distribution of the source region and drain region formed by the ion implantation has a partial peak at a predetermined depth from the surface. The ion implantation is performed such that the ion implantation takes a value low enough to prevent short-circuiting between the source region and drain region and the shot gate electrode at the surface.

[Industrial application field]

The present invention is a shotgun using compound semiconductors.
This invention relates to improvements in methods for manufacturing semiconductor devices such as gate field effect transistors.

For example, the gate electrode in a GaAs shot gate field effect transistor can be made of aluminum (Al), gold (Au), titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta).
Metals such as are used. However, heat treatment at about 600 degrees Celsius degrades the electrical characteristics of the gate electrode, such as barrier height, n value (1.04), and reverse breakdown voltage, making it impossible to operate as a transistor.

Therefore, there is a need for a gate electrode whose characteristics do not deteriorate even when subjected to such heat treatment.

[Conventional technology]

In recent years, gate electrodes made of TiW have been announced as a device that can meet the above requirements.

[Problem to be solved by the invention]

Gate electrodes made of TiW are able to withstand higher temperatures than conventional gate electrodes, but when subjected to heat treatment below, for example, 850 [°C], the shot barrier is lost. As a result, the operation of the field effect transistor becomes unstable.

Further, if a normal manufacturing process is applied, the resistivity may increase or be lost due to corrosion during the process.

The present invention makes it possible to manufacture a semiconductor device having a shot gate electrode that can withstand heat treatment at 850[° C.] or higher.

In the present invention, "shot contact" refers to a situation in which the electrode metal directly contacts the semiconductor substrate and diode characteristics occur, and a situation in which the electrode metal directly contacts the semiconductor substrate and an alloy is formed between the electrode metal and the semiconductor substrate. This includes those in which diode characteristics occur, and those in which electrode metal is disposed through a natural oxide film on the surface of a semiconductor substrate and diode characteristics occur due to tunneling in the natural oxide film.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a shot gate electrode made of silicide containing tungsten on a compound semiconductor, and then implanting impurity ions using the shot gate electrode as a mask. Shotsutoki・
A step of forming a source region and a drain region on both sides of the gate electrode, a step of performing high temperature heat treatment to activate the implanted impurities, and then forming an electrode of a predetermined material on the source region and the drain region. The impurity concentration distribution of the source and drain regions formed by the ion implantation has a peak value at a predetermined depth from the surface, and the impurity concentration distribution of the source and drain regions formed by the ion implantation has a peak value at a predetermined depth from the surface, and The ion implantation is performed such that the ion implantation takes a low value to the extent that no short circuit occurs between the shot and the gate electrode.

[Effect]

By adopting the above-mentioned means, the positioning of the shot gate electrode can be performed in a self-aligned manner, and even if this is done, short circuits will not occur between the source region and the drain region and the shot gate electrode. .

〔Example〕

1 to 6 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.

See Figure 1 (1)-1 For example, semi-insulating material doped with chromium (Cr)
A silicon dioxide (SiO ₂ ) film 2 having a thickness of, for example, about 6000 Å is formed on a GaAs substrate 1 .

(1)-2 By applying ordinary photolithography technology, the silicon dioxide film 2 is patterned to form the window 2a.

(1)-3 By applying the ion implantation method, silicon ions are implanted at a dose of 2.6×10 ¹² [cm ⁻² ].

See FIG. 2 (2)-1 After removing the silicon dioxide film 2, a new silicon dioxide film (not shown) with a thickness of, for example, about 1000 Å is formed to prevent out-diffusion.

(2)-2 Set the temperature to e.g. 850 [℃] and the time to e.g.
Heat treatment is performed for 15 [minutes]. Depending on this,
An n-type layer 3 as shown can be obtained.

(2)-3 Remove the divalent silicon film for preventing the outward diffusion.

See Figure 3 (3)-1 A TiWSi alloy, for example an alloy consisting of Ti _0.3 W _0.7 Si _2, is deposited by sputtering to a thickness of 6000 mm, for example.
An alloy film of [Å] is formed.

(3)-2 The gate electrode 4 is formed by patterning the alloy film by applying a dry etching method using CF ₄ +O ₂ (5%) as an etching gas.

See FIG. 4 (4)-1 A silicon dioxide film 5 is formed by applying a conventional technique.

(4)-2 By applying a conventional technique, the silicon dioxide film 5 is selectively etched to form the window 5a.
form.

(4)-3 By applying the ion implantation method, the dose was reduced to 1.7×10 ¹³ [cm ^-2 ] and the acceleration energy was reduced to 175
Inject Si as [KeV].

See FIG. 5 (5)-1 After removing the silicon dioxide film 5, a new silicon dioxide film (not shown) with a thickness of, for example, about 1000 Å is formed to prevent out-diffusion.

(5)-2 Set the temperature to e.g. 800 [℃] and the time to e.g.
Heat treatment is performed for 15 [minutes].

As a result, n ⁺ type regions 6 and 7 as shown can be obtained.

(5)-3 Remove the divalent silicon film for preventing the outward diffusion.

n ⁺ type regions 6 and 7 formed in this step
The impurity concentration is 1×10 ¹⁸ [cm
^-3 ], and that of n-type layer 3 was also 1×10 ¹⁷ [cm ^-3 ] at the peak portion.

Refer to Figure 6 (6)-1 If necessary, remove the surface of the GaAs part by 100%.
Etch approximately [Å]. Note that KOH+H ₂ O ₂ may be used as the etching solution at this time.

(6)-2 Complete by forming electrodes 8 and 9 on n ⁺ type regions 6 and 7 by applying a conventional technique. Note that AuGe/Au type may be used as the electrode material.

Specific data regarding the semiconductor device manufactured in this manner is as follows.

Gate length: 1.4 [μm] Gate width: 200 [μm] Source-drain distance: 6 [μm] Mutual conductance g _n : 23 [mS] Source-gate capacitance C _gs : 0.21 [pF] Cut-off frequency f _T : 12.3 [CHHz] N value for shot gate: 1.18 Barrier height: 0.78 Breakdown voltage: 10 [V] By the way, in the present invention, n ⁺ type regions 6 and 7
is formed by a self-alignment method using the shot gate electrode 4 as a mask, so normally there would be a concern about short circuit between the shot gate electrode 4 and the n ⁺ type regions 6 and 7, but this No problem at all. That is, as described above, the n ⁺ type region 6 is formed by applying ion implantation method or the like.
7 is formed, the impurity concentration distribution there becomes a Gaussian distribution as shown in Fig. 7, and a peak is generated at a depth of, for example, 0.15 [μm], where the impurity concentration is 1×10 ¹⁸ [cm ^-3 ]. If the voltage is about 1×10 ¹⁷ [cm ^-3 ] at the surface, a breakdown voltage of 5 [V] or more can be obtained. Furthermore, as described in step (6)-1, when the surfaces of the n ⁺ type regions 6 and 7 are etched, as is clear from FIG. lower than the interface with
The withstand pressure becomes even higher.

In order to maintain the reverse breakdown voltage at the shot gate electrode, the following measures may be taken.

(a) Decrease the dose of n ⁺ type regions 6 and 7.

(b) After forming the n ⁺ type regions 6 and 7, the shot gate electrode 4 is etched to be thin.

(c) Insulating the short gate electrode 4.

(d) Etching the surfaces of n ⁺ type regions 6 and 7.

(e) Before forming the n ⁺ -type regions 6 and 7, the shot gate electrode 4 serving as a mask is processed into an umbrella shape, or a mask constituting an umbrella shape is provided separately, and then ion implantation is performed.

(f) Increase the ion implantation energy to deepen the project range.

In the present invention, the above-mentioned means (f) is basically adopted, but other means may be used in combination as necessary, and in the above embodiment, the above-mentioned means (f) and (d) It is used in conjunction with means. Note that the method (d) has the advantage of being relatively easy to implement and relatively highly effective compared to other methods.

Incidentally, data regarding the shot reverse breakdown voltage in the GaAsn ⁺ type region is as follows.

When the impurity concentration is 2×10 ¹⁸ [cm ^-3 ] -1 For an n ⁺ type flat layer formed by epitaxial growth etc., it is 0.85 [V] -2 For an n ⁺ type layer with Gaussian distribution due to Si ion implantation. , E: 175 [KeV], R _P :
If 0.150 [μ], then 3.65 [V] -3 At -2, E: 350 [KeV], R _P :
0.306 [μ] is 7.77 [V] If the impurity is 1 × 10 ¹⁸ [cm ^-3 ] -1 For an n ⁺ type flat layer formed by epitaxial growth, it is 1.69 [V] -2 Gaussian due to Si ion implantation It is an n ⁺ type layer having a distribution, E: 175 [KeV], R _P :
If 0.15 [μ], then 5.27 [V] -3 -2, E: 350 [KeV], R _P :
If it is 0.306 [μ], it will be 10.2 [V]. If the impurity concentration is 5 × 10 ¹⁷ [cm ^-3 ], -1. If the n ⁺ type flat layer is formed by epitaxial growth, it will be 3.39 [V] -2 if it is by Si ion implantation. It is an n ⁺ type layer with Gaussian distribution, E: 175 [KeV], R _P :
If 0.150 [μ], then 7.50 [V] -3 At -2, E: 350 [KeV], R _P :
0.306 [μ] is 13.3 [V] By the way, in the present invention, the position of the shot gate electrode can be determined by self-alignment, that is, the ion implantation is performed after forming the shot gate electrode, and its activation is determined. The ability to perform chemical heat treatment is largely due to the use of high melting point metal silicide as the electrode material, so we will discuss it here.
Comparing data between TiW and TiWSi is as follows.

A Specific resistance (after heat treatment at 850 [℃], 15 [minutes]) A-1 TiW (Ti: 10 [wt%], 2 to 3 ×
10 ⁴ [Ω・cm] A-2 Ti _x W _1-X Si ₂ (Ti: 10 [wt%]), 0.8 to 1×10 ^-4 [Ω・cm] B Corrosion against HF [conc] B- 1 In TiW (Ti: 10 [wt%]), 1 [μ
m/min] B-2 Ti _x W _1-x Si ₂ (Ti: 10 [wt%]), 1900 [Å/min] C _- 1 TiW (Ti : 10 [wt%]), 1200 [Å/min] C-2 T _x W _1-x Si ₂ (Ti: 10 [wt%]), 267 [Å/min] D 850 [℃], 15 Shock bonding stability after heat treatment for [minutes] D-1 TiW (Ti: 10 [wt%], approximately 50 [%])
In D-2 Ti _x W _1-x Si ₂ (Ti: 10 [wt%]), the shot resistance is stable at about 100 [%] Barrier height: 0.78 [V] n value: 1.18 In the example, as a material for the gate electrode
TiWSi was used, but in this composition, Ti is GaAs
This element is included for the purpose of improving the adhesion to the metal, but it can be made unnecessary by optimizing the composition ratio of W and Si to improve the adhesion.

In the present invention, the composition of the alloy film is not limited to a stoichiometric alloy, and may be slightly different from the stoichiometric value.

〔Effect of the invention〕

In the method for manufacturing a semiconductor device according to the present invention, a shot gate electrode made of silicide containing tungsten is formed on a compound semiconductor, and impurity ions are implanted using the shot gate electrode as a mask to form the shot gate electrode. forming source and drain regions on both sides of the electrode, performing high temperature heat treatment to activate the implanted impurities;
Electrodes made of a predetermined material are formed on the source region and drain region, and the impurity concentration distribution of the source region and drain region formed by the ion implantation has a peak value at a predetermined depth from the surface, and at the surface. The ion implantation is performed so that the value is low enough to prevent short circuit between the source region and drain region and the shot gate electrode.

By employing the above configuration, the positioning of the shot gate electrode can be performed in a self-aligned manner, and even if this is done, short circuits will not occur between the source region and the drain region and the shot gate electrode. , Therefore, it is effective for highly integrating semiconductor devices made of compound semiconductors.

[Brief explanation of drawings]

1 to 6 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIG. 7 is a diagram for explaining impurity concentration distribution. ing. In the figure, 1 is a substrate, 2 is a silicon dioxide film, 3 is an n-type layer, 4 is a gate electrode, 6 and 7 are
The n ⁺ type regions, 8 and 9, respectively indicate electrodes.

Claims (1)

[Claims] 1. A step of forming a shot gate electrode made of silicide containing tungsten on a compound semiconductor, and then implanting impurity ions on both sides of the shot gate electrode using the shot gate electrode as a mask. The method includes a step of forming a source region and a drain region, a step of performing high temperature heat treatment to activate the implanted impurities, and a step of forming an electrode of a predetermined material on the source region and the drain region. The impurity concentration distribution of the source region and drain region formed by the ion implantation has a peak value at a predetermined depth from the surface, and at the surface, the impurity concentration distribution of the source region and drain region and the shot gate electrode A method of manufacturing a semiconductor device, characterized in that the ion implantation is performed such that the values of and are low enough to prevent short circuits.