JPH0249434A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a short-circuit between source and drain regions and a gate electrode by a method wherein when an impurity is implanted using the Schottky gate electrode as a mask to form the source and drain regions, the impurity is implanted in such a way that the impurity concentration distribution is given the peak value in a prescribed depth from the surface. CONSTITUTION:Si ions are selectively implanted in a GaAs substrate 1 and thereafter, a heat treatment is performed to obtain an n-type layer 3. Then, a TiWSi alloy film is adhered and is etched to form a gate electrode 4. Subsequently, Si is ion-implanted using an SiO2 film 5 formed selectively and the electrode 4 as masks. At this time, an impurity is implanted in such a way that the impurity concentration is given the peak value in a prescribed depth from the surface. Then, after the film 5 is removed, a heat treatment is performed to form n<+> source and drain regions 6 and 7. Electrodes 8 and 9 are formed on the regions 6 and 7. In such a way, a short-circuit between the regions 6 and 7 and the electrode 4 can be prevented and an increase in integration becomes possible.

Description

[Detailed Description of the Invention] [Summary] A Schottky gate electrode that can withstand heat treatment of 850 (°C) or more is related to an improvement in the method of manufacturing semiconductor devices such as Schottky gate field effect transistors using compound semiconductors. The purpose of this process is to form a Schottky gate electrode made of silicide F containing tungsten on a compound semiconductor, and then ion-implant impurities using the Schottky gate electrode as a mask. A step of forming a source region and a drain region on both sides of the Schottky gate electrode, a step of performing high temperature heat treatment to activate the implanted impurities, and a step of forming a predetermined material on the source region and drain region. the impurity concentration distribution of the source region and drain region formed by the ion implantation has a peak value at a predetermined depth from the surface, and at the surface, the impurity concentration distribution of the source region and the drain region The ion implantation is performed so that the value of the ion implantation is low enough to prevent a short circuit between the drain region and the Schottky gate electrode.

[Industrial application field]

The present invention relates to improvements in methods for manufacturing semiconductor devices, such as Schottky gate field effect transistors, using compound semiconductors.

For example, aluminum (Aβ) is used as the gate electrode in a GaAs Schottky gate field effect transistor.
, gold (Au), titanium (Ti), molybdenum (Mo),
Metals such as tungsten (W) and tantalum (Ta) are used. However, heat treatment at about 600°C deteriorates the electrical properties of the gate electrode, such as barrier height, n value (1,04), and reverse breakdown voltage, making it impossible to operate as a transistor. become.

Therefore, there is a need for a gate electrode whose characteristics do not deteriorate even when subjected to such heat treatment.

[Conventional technology]

In recent years, Ti has been developed as a material that can meet the above requirements.
Gate electrodes made of W have been announced.

[Problem to be solved by the invention]

Although the gate electrode made of TiW can withstand higher temperatures than conventional gate electrodes,
For example, when heat treated at 850° C. or higher, the Schottky barrier is lost and the operation of the field effect transistor becomes unstable.

Further, if a normal manufacturing process is applied, the resistivity may increase or be lost due to corrosion during the process.

The present invention makes it possible to manufacture a semiconductor device having a Schottky gate electrode that can withstand heat treatment of 850 ('C) or higher.

In the present invention, Schottky contact is defined as one in which the electrode metal directly contacts the semiconductor substrate and diode characteristics occur, or one in which the electrode metal directly contacts the semiconductor substrate and an alloy is formed between the electrode metal and the semiconductor substrate. Those that exhibit diode characteristics,
This includes a structure in which an electrode metal is disposed through a natural oxide film on the surface of a semiconductor substrate and diode characteristics are generated by a tunneling phenomenon in the natural oxide film.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a Schottky gate electrode made of silicide containing tungsten on a compound semiconductor, and then implanting impurity ions using the Schottky gate electrode as a mask. forming source and drain regions on both sides of the Schottky gate electrode, then performing a high temperature heat treatment to activate the implanted impurities;
forming an electrode of a predetermined material on the source region and drain region, the impurity concentration distribution of the source region and drain region formed by the ion implantation is at a predetermined depth from the surface. The ion implantation is performed so as to have a peak value and a value low enough to prevent short-circuiting between the source and drain regions and the Schottky gate electrode at the surface.

[Effect]

By adopting the above-mentioned means, the Schottky gate electrode can be positioned in a self-aligned manner, and even in this case, short circuits between the source region and the drain region and the Schottky gate electrode will not occur. .

〔Example〕

1 to 6 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.

See FIG. 1 (fkl) A silicon dioxide (SiOz) film 2 having a thickness of, for example, about 6,000 [people] is formed on a semi-insulating GaAs substrate 1 doped with, for example, chromium (Cr).

The silicon dioxide film 2 is patterned to form the window 2a by applying a normal photolithography technique.

By applying the ion implantation method, the dose can be reduced to 2.
Silicon ions are implanted as 6xl O'' (C1l-Snow).

After removing the silicon dioxide film 2 (see FIG. 2), a new silicon dioxide film (not shown) is formed to a thickness of, for example, about 1000 cm for preventing out-diffusion.

Set the temperature to, for example, 850 ('C), and set the time to, for example, 15
Heat treatment is performed for [minutes]. With this, an n-type layer 3 as shown in the figure can be obtained.

The silicon dioxide film for preventing the out-diffusion is removed.

See Figure 3 TiWSi alloy, for example T '13 wo,? Si
An alloy film consisting of T is deposited by sputtering to form an alloy film having a thickness of, for example, 6,000 mm.

The gate electrode 4 is formed by patterning the alloy film by applying a dry etching method using CF4+Ot (5(%)) as an etching gas.

By applying conventional techniques, see FIG. 4, a silicon dioxide film 5
form.

By applying conventional techniques, a silicon dioxide film 5
Selective etching is performed to form the window 5a.

By applying the ion implantation method, the dose can be reduced to 1.
7 x 10I3 (3-”) and acceleration energy 175
(KeV), Si is implanted.

After removing the silicon dioxide film 5 (see FIG. 5), a new silicon dioxide film (not shown) is formed to a thickness of, for example, about 1,000 mm for preventing out-diffusion.

Set the temperature to, for example, 800 ('C), and set the time to, for example, 15
Heat treatment is performed for [minutes].

As a result, n+ type regions 6 and 7 as shown in the figure can be obtained.

The silicon dioxide film for preventing the out-diffusion is removed.

The impurity concentration of the n+ type regions 6 and 7 formed in this step is I x 10''(am-') at the peak portion, and that of the n-type layer 3 is also 1 x 10 ” (am-') at the peak portion.
” (co+-').

Refer to FIG. 6. If necessary, the surface of the GaAs portion is etched by about 100 mm. In addition, the etching solution used at this time is KOH+H! You can use O.

By applying conventional techniques, the n+ type regions 6 and 7 are
Electrodes 8 and 9 are formed on top to complete the process. Note that as the electrode material, A u G e / A u type may be used.

- Specific data regarding the semiconductor device manufactured in this manner is as follows.

Gate length: 1.4 (μm) Gate radius: 200 (μm) Source-drain distance = 6 [μm] Mutual conductance g: 23 (ms) Source-gate capacitance C1: 0.21 (pF) Cutoff frequency fr
: 12. 3 (GHz) Schottky gate n value: 1.18 Barrier hide: o,'ys Breakdown voltage: 10 (V) By the way, in the present invention, the Schottky gate electrode 4 is masked in the n+ type regions 6 and 7. Since it is formed using a self-aligned method, normally there would be a concern that there would be a short circuit between the Schottky gate electrode 4 and the n+ type regions 6 and 7, but this is not a problem at all. That is, as described above, when the n+ type regions 6 and 7 are formed by ion implantation or the like, the impurity concentration distribution there becomes a Gaussian distribution as shown in FIG. It is generated at 0.15 (μm), where I
If it is about 10” (cm-”), I
When the voltage is about IO"(cm-"), a breakdown voltage of 5 [73 or more] can be obtained. Furthermore, as described in step (6)-1, when the surfaces of the n+ type regions 6 and 7 are etched, as is clear from FIG. The breakdown voltage becomes lower than that at the interface between the two and the breakdown voltage becomes even higher.

The following measures may be taken to maintain the reverse breakdown voltage of the Schottky gate electrode.

(The dose amount of the al n+ type regions 6 and 7 is lowered.

(After forming the n+ type regions 6 and 7, the Schottky gate electrode 4 is etched to make it thinner.)

(C1 Shore) The key gate electrode 4 is insulated.

(dl Etch the surfaces of n+ type regions 6 and 7.

(e) Before forming the n+ type regions 6 and 7, the Schottky gate electrode 4 serving as a mask is processed into an umbrella shape, or a mask constituting an umbrella shape is provided separately, and then ion implantation is performed.

(f) Increasing the energy of ion implantation to deepen the project range.

In the present invention, the above-mentioned means (f) is basically adopted, but other means may be used in conjunction with the above-mentioned means (f) as needed. It is used in conjunction with means. Note that the method (d) has the advantage of being relatively easy to implement and relatively highly effective compared to other methods.

By the way, Qa71. Data regarding the Schottky reverse breakdown voltage for the sn+ type region is as follows.

■ When the impurity concentration is 2X10" (am arch) ■ For an n++ flat layer formed by -1 epitaxial growth, etc., it is 0.85
(V) ■n with Gaussian distribution due to −2Si ion implantation
+ type layer, E: 175 (KeV), Rp: 0
．． 150 (/j) then 3.65 (V) ■-3■-2 E: 350 (KeV), R,
:Q, 306 (μ): 7.77 (V) ■ When the impurity concentration is I x 10 ” (ell-”) ■ -1 For an n++ flat layer formed by epitaxial growth, etc., it is 1.69 (V) ■ - n with Gaussian distribution due to 2Si ion implantation
+ type layer, E: 175 (KeV), Rp: Q
, 150 (μ), then 5.27 [V) ■-3■-2, E: 350 (KeV), R,
:0.306 Cμ] is 10.2 (V) ■ If the impurity concentration is 5 × I Q ” (am-”) ■ -1 For an n++ flat layer formed by epitaxial growth, it is 3.39 (V) ■ - n with Gaussian distribution due to 2Si ion implantation
+ type layer, E: 175 (KeV), RP C
0,150Cμ)"i? 7.50 (V) ■-3■-2 E:350 (KeV), RF
:0.306 Cμ] is 13.3 (V) By the way, in the present invention, the position of the Schottky gate electrode can be determined by self-alignment.
The ability to perform ion implantation and activation heat treatment after forming the gate electrode is largely due to the use of high melting point metal silicide as the electrode material, so we will compare TiW and TiWSi here. The data are shown below.

A Specific resistance (850 ('C), after heat treatment for 15 minutes) A-I TiW (Ti: 10 (wt%)), 2
~3X10' (Ω・1) A 2 Tl)l Wl-X S lz (Tt
: 10 (wt%)), 0.8~lXl0-' (Ω・value) B-I Ti Ti
For W (Ti: 10 (weight%)), 1 [μm/
minutes] B-2TixW, -x Sit (Ti: 10 (
(wt%)), 1900 (people/min) Corrosion C-IT for CNH,F:HF=lO:1
iW (Ti: 10 C weight %) is 1200
[Person/min] C-2Ti, IW+-3iz (Ti: 10 (
Schottky bond stability after heat treatment of 267 [people/min] D 850 ('C), 15 (min) DI TiW (Ti: 10 (wt%)), approximately 50 [%] ] deteriorates and becomes unstable D-2Tiz Wl-x S it (Ti: 1
0 (wt%), approximately 100% is stable Schottky characteristic Barrier hide: 0.78 (v) n value: 1.18 In the above example, TiWS was used as the material of the gate electrode.
In this composition, Ti was included for the purpose of improving the adhesion to GaAs, and this was done by optimizing the composition ratio of W and Si to improve the adhesion. It can be made unnecessary.

In the present invention, the composition of the alloy film is not limited to a stoichiometric alloy, and may be slightly different from the stoichiometric value.

〔Effect of the invention〕

In the method for manufacturing a semiconductor device according to the present invention, a Schottky gate electrode made of silicide containing tungsten is formed on a compound semiconductor, and impurity ions are implanted using the Schottky gate electrode as a mask to form the Schottky gate electrode. Forming a source region and a drain region on both sides of the electrode, performing high temperature heat treatment to activate the implanted impurities, forming an electrode of a predetermined material on the source region and drain region, and forming it by the ion implantation. The impurity concentration distribution of the source region and the drain region obtained by the above-mentioned method has a peak value at a predetermined depth from the surface, and the impurity concentration distribution at the surface has a low value to the extent that no short circuit occurs between the source region and the drain region and the Schottky gate electrode. The ion implantation is carried out to ensure that

By employing the above configuration, the Schottky gate electrode can be positioned in a self-aligned manner, and even if this is done, short circuits will not occur between the source region and the drain region and the Schottky gate electrode. Therefore, it is effective for highly integrating semiconductor devices made of compound semiconductors.

[Brief explanation of the drawing]

1 to 6 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIG. 7 is a diagram for explaining impurity concentration distribution. ing. In the figure, 1 is a substrate, 2 is a silicon dioxide film, 3 is an n-type layer, 4 is a gate electrode, 6 and 7 are n+ type regions 8 and 9 are electrodes, respectively. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 2 Figure 5 Figure 6 Figure 3 Figure 4 Diagram for explaining impurity concentration distribution Figure 7

Claims (1)

[Claims] A step of forming a Schottky gate electrode made of silicide containing tungsten on a compound semiconductor, and then ion-implanting impurities using the Schottky gate electrode as a mask and depositing sources on both sides of the Schottky gate electrode. The method includes a step of forming a region and a drain region, a step of performing high temperature heat treatment to activate the implanted impurity, and a step of forming an electrode of a predetermined material on the source region and the drain region. Therefore, the impurity concentration distribution of the source region and drain region formed by the ion implantation has a peak value at a predetermined depth from the surface, and the source region and drain region and the Schottky gate electrode have a peak value at the surface. A method of manufacturing a semiconductor device, characterized in that the ion implantation is carried out so that the value of is low enough not to cause a short circuit.