JPH0358743U - - Google Patents
Info
- Publication number
- JPH0358743U JPH0358743U JP6040790U JP6040790U JPH0358743U JP H0358743 U JPH0358743 U JP H0358743U JP 6040790 U JP6040790 U JP 6040790U JP 6040790 U JP6040790 U JP 6040790U JP H0358743 U JPH0358743 U JP H0358743U
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- parity
- memory
- address decoder
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案による第１の実施例を示すブロ
ツク構成図、第２図は本考案による第２の実施例
を示すブロツク構成図、第３図は従来の技術を示
すブロツク図である。
１，２１……マイクロプロセツサ（ＭＰＵ）、
２，２２……アドレスデコーダ、３……多数決処
理部、４，５，６，２４……ＲＯＭ、１３……選
択部、１４，１５，…，１６……メモリ、１７…
…パリテイチエツク部、１８……パリテイ用メモ
リ。
FIG. 1 is a block diagram showing a first embodiment according to the present invention, FIG. 2 is a block diagram showing a second embodiment according to the present invention, and FIG. 3 is a block diagram showing a conventional technique. 1, 21...Microprocessor (MPU),
2, 22...address decoder, 3...majority processing unit, 4, 5, 6, 24...ROM, 13...selection unit, 14, 15,..., 16...memory, 17...
...Parity check section, 18...Memory for parity.
Claims (1)
とする蓄積プログラム方式の制御装置において、
マイクロプロセツサと、該マイクロプロセツサか
らのアドレスをデコードするアドレスデコーダと
、該アドレスデコーダの同一出力で同時に読出し
が行われる３個のＲＯＭと、該３個のＲＯＭの出
力を比較して、２個以上のデータの一致を検出し
その一致データを前記マイクロプロセツサに供給
する多数決処理部とを含むことを特徴とするメモ
リアクセス回路。 (2) マイクロプロセツサとメモリとを構成要素
とする蓄積プログラム方式の制御装置において、
マイクロプロセツサと、該マイクロプロセツサか
らのアドレスをデコードするアドレスデコーダと
、該アドレスデコーダの同一アドレスにマツピン
グされた２組以上のメモリと、該複数組のメモリ
のアドレス単位にパリテイチエツクを行うパリテ
イチエツク手段と、メモリ書込み時に前記パリテ
イチエツク手段によりチエツクされた該パリテイ
を記憶するパリテイ記憶手段と、メモリ読出し時
に行われる前記パリテイチエツク手段によるパリ
テイチエツクの結果により前記複数組のメモリの
出力から１組を選択する選択手段とを有すること
を特徴とするメモリアクセス回路。[Claims for Utility Model Registration] (1) In a storage program type control device comprising a microprocessor and a memory,
A microprocessor, an address decoder that decodes the address from the microprocessor, and three ROMs that are simultaneously read out using the same output from the address decoder are compared, and the outputs of the three ROMs are compared. 1. A memory access circuit comprising: a majority decision processing section which detects coincidence of data of at least one memory and supplies the coincidence data to the microprocessor. (2) In a storage program type control device whose components include a microprocessor and a memory,
A microprocessor, an address decoder that decodes addresses from the microprocessor, two or more sets of memories mapped to the same address of the address decoder, and a parity check performed in units of addresses of the plural sets of memories. parity checking means; parity storage means for storing the parity checked by the parity checking means at the time of memory writing; and parity storage means for storing the parity checked by the parity checking means at the time of memory reading; and selecting means for selecting one set from the outputs of the memory access circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6040790U JPH0358743U (en) | 1989-06-09 | 1990-06-07 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6780389 | 1989-06-09 | ||
| JP6040790U JPH0358743U (en) | 1989-06-09 | 1990-06-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0358743U true JPH0358743U (en) | 1991-06-07 |
Family
ID=31718233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6040790U Pending JPH0358743U (en) | 1989-06-09 | 1990-06-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0358743U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998029814A1 (en) * | 1996-12-26 | 1998-07-09 | Rohm Co., Ltd. | Ic card |
| WO2002041152A1 (en) * | 2000-11-16 | 2002-05-23 | Niigata Seimitsu Co., Ltd. | Memory system |
| JP2002360338A (en) * | 2001-06-12 | 2002-12-17 | Takashi Kosako | Cleansing cotton |
| JP5575997B1 (en) * | 2013-03-13 | 2014-08-20 | 長瀬産業株式会社 | Semiconductor device and entry address writing / reading method for semiconductor device |
-
1990
- 1990-06-07 JP JP6040790U patent/JPH0358743U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998029814A1 (en) * | 1996-12-26 | 1998-07-09 | Rohm Co., Ltd. | Ic card |
| WO2002041152A1 (en) * | 2000-11-16 | 2002-05-23 | Niigata Seimitsu Co., Ltd. | Memory system |
| JP2002360338A (en) * | 2001-06-12 | 2002-12-17 | Takashi Kosako | Cleansing cotton |
| JP5575997B1 (en) * | 2013-03-13 | 2014-08-20 | 長瀬産業株式会社 | Semiconductor device and entry address writing / reading method for semiconductor device |
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