JPH035953Y2 - - Google Patents

Description

[Detailed description of the invention] [Summary] Regarding a scan-out circuit for knowing the status of hardware (latches, gates) constituting a data processing device, the scan-out circuit of any logic element in the data processing device can be controlled by the circuit. The purpose is to provide a circuit that can perform all operations using logical values so as not to be confused by polarity.The scan-out address includes a part of the scan-out address that indicates whether the logic element corresponding to that address is positive logic or negative logic. At the output section of the scan-out mechanism, a polarity flag indicating whether the scan-out result sent from the specific device is exclusive to the polarity flag in the scan-out address corresponding to the scan-out address is added. A circuit that takes an OR and decodes the device specified address of the scan-out address, and when the power of the selected device is off, the scan-out result of the selected device is forcibly set to logic "0". The configuration is such that a circuit such as this is provided.

[Industrial application field]

2. Description of the Related Art As data processing devices have recently become larger in scale and more highly integrated, various methods have been devised as testing and diagnostic functions to search for hardware failures, one of which is a scan-in-out function. This is to first put the data processing device in scan-in-out mode, give scan addresses to the latches and gates that make up the data processing device, give data from the outside (for example, a service processor) (called scan-in), and read it. (referred to as scanout), said latch;
It is possible to check the status of the gate and use the results to search for failures in the data processing device.

[Problems to be solved by conventional technology and invention]

However, in general, the polarity of the output of each logic element constituting a data processing device differs depending on each element, and in one logic stage, the positive polarity is logic "1", and in another logic stage, the negative polarity is logic "1". 1'', and it is difficult to determine whether correct logical operation is occurring by simply looking at the scan-out data of the logic elements constituting the data processing device.

In view of this situation, it is desired to improve the so-called scan-in-out function.

Figure 1 shows the data processing device (hereinafter referred to as CPU)
This is a block diagram showing the scan-out function, in particular, among the conventional scan-in-out functions provided in When a scan-out address is given from the processor (not shown) to the scan-out control circuit 13 of the CPU 1, it is set in the scan-out address register (SADR) 131, decoded by the decoder 132, and output signal a from the scan-out address register (SADR) 131. Then, the AND circuit 121 constituting the multiplexer 12 is gated, and the output of the latch 11, which is one of the latches constituting the CPU 1, is input to the OR circuit 122, and the output is sent to the scan-out register of the scan-out control circuit 13. (SR) 133 and can be read out to the service processor as a scanout value.

However, the output of the latch corresponding to the scan-out address is not related to its logic polarity, and simply outputs the value of the logic element at that time. )
There was a problem in which it was not possible to scan out based on the method, and it was not possible to make correct decisions. Particularly, when the data processing device is powered off, the scan-out data of the data processing device shows a specific logical value even though it is undefined, leading to a problem of erroneous judgment.

[Means for Solving the Problems] In view of the above-mentioned conventional drawbacks, the present invention makes it possible to scan out any logic element in a data processing device using logical values without being confused by the polarity of the circuit. The purpose is to provide a circuit.

According to the present invention, in the scan-out function for knowing the state of the hardware constituting the data processing device, the scan-out address includes a part of the scan-out address indicating whether the logic element corresponding to the address is positive logic. , a polarity flag indicating whether it is a negative logic is added, and the scan-out result sent from the specific device and the polarity in the scan-out address are added to the output section of the scan-out mechanism, corresponding to the scan-out address. A circuit that takes an exclusive OR with the flag and decodes the device specified address of the scan-out address, and when the power of the selected device is off,
This is achieved by providing a circuit that forces the scan-out result of the device to be logic "0".

[Effect]

According to the present invention, the scan-out data and the polarity flag are non-transitively ORed, and the result is logically ANDed with the power-on signal of the scan-out target device to obtain the scan-out result. This eliminates the need for the scan-out program to check the polarity of the logic element and whether the power is turned on or off, and the state of the logic element can be correctly determined.

〔Example〕

The present invention will be explained in detail below with reference to the drawings. FIG. 2 is a block diagram showing the scanout function according to the present invention, in which 1 is a data processing device, 2 is a scanout control section in a service processor, 21 is a scanout address register (SADR), 22 and 23 are selection circuits having a multiplexer configuration, 24 is a non-alternative OR circuit, and 25 is an AND circuit. The scan-out address register 21 is a scan-out address section 21 within the device.
1, a device specification address field 212, and a polarity flag 213 related to the present invention. This polarity flag 213 indicates whether the logic element corresponding to the scan-out address is a positive logic element or a negative logic element, and in the case of positive logic, a "1" level indicates the presence of a signal; In the case of negative logic, a "0" level indicates the presence of a signal.

Now, when the scan-out address is sent from the scan-out control unit 2 of the service processor (not shown) to the scan-out compatible device, the in-device scan-out address unit 211 sends the scan-out address to the corresponding logic element in each device. The output is sent to the selection circuit 23 of the scanout control section 2. Selection circuit 23
Then, scan-out data of a specific device is selected by the device-specified address section 212 of the scan-out address register 21, and its output is sent to one input of the exclusive OR circuit 24. The other input of the exclusive OR circuit 24 is connected to the polarity flag 213 of the scan-out address register 21.
It is understood that since the exclusive OR circuit 24 calculates the exclusive OR, it is possible to perform scan-out using a logic value that is not affected by the polarity of the logic element.

In this embodiment, the device specification address field 2
Since the selection circuit 22 is controlled by 12,
The on/off state of the power supply of the device is output and gates the AND circuit 25. As a result, when the device is powered on, the scan-out output of the exclusive OR circuit 24 is output as scan-out data, but when the device is powered off, the scan-out output of the exclusive OR circuit 24 is output as scan-out data. Outputs logic "0" regardless of the out output. Therefore, even if a device whose power is not turned on is scanned out, the states of the logic elements are all "0" and no erroneous judgment will be made.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the polarity flag is included in the scanout address and sent to the scanout control unit 2, and the scanout control unit 2 receives the scanout data from the specific device and the polarity flag. The result is ANDed with the power-on signal of the specific device to obtain the scan-out result. Furthermore, when the power of the device to be scanned out is off, the AND circuit 25 of the scanout control unit 2 forcibly sets the logic to "0", so that the program for scanout can control the polarity of the logic element and the power supply. There is no need to check whether the logic element is on or off, and scanout of any logic element within the data processing device can be performed based on the logic value, making it possible to correctly determine the state of the logic element.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional scan-out function, and FIG. 2 is a diagram showing an embodiment of the present invention. In the figure, 1 is a data processing device, 2 is a scan-out control section, 21 is a scan-out address register, 22 and 23 are selection circuits, 24 is an exclusive OR circuit, and 25 is an AND circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] In a data processing device having a scan-out function, a polarity flag indicating whether the logic element corresponding to the address is positive logic or negative logic is included in a part of the scan-out address. Additionally, in the output section of the scan-out mechanism, a circuit that performs an exclusive OR of the scan-out result sent from the specific device and the polarity flag in the scan-out address corresponding to the previous scan-out address; and a circuit that decodes the device specified address of the scan-out address and forcibly sets the scan-out result of the selected device to logic "0" when the power of the selected device is off. Features a scan-out circuit.