JPH11203162A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To improve the efficiency when evaluating the output driver capability of an output terminal. SOLUTION: Based on a signal input from a test input terminal, test output data for determining an output of an output terminal and an input / output terminal from an output driver is generated and output, and the output terminal and the input / output are output. A test control logic for generating and outputting a control signal for obtaining the output from a terminal, a test output data holding circuit for holding the test output data output from the test control logic, and a test output data holding circuit The output terminal based on the test output data and the control signal held at
A selection switching circuit is provided for simultaneously obtaining the output from all of the input / output terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device capable of easily testing a drive capability of an output terminal or an input / output terminal.

[0002]

2. Description of the Related Art When measuring the output drive capability of an output terminal or an input / output terminal provided in a conventional semiconductor integrated circuit device (LSI or the like) such as a single-chip microcomputer, the microcomputer is operated according to a program and built-in. The test data is set in the memory or the register, and the output drive capability of the output terminal or the input / output terminal is measured. FIG. 6 is a block diagram showing a configuration of a test circuit for measuring the output drive capability of the output terminal or the input / output terminal. FIG.
, 51 is a semiconductor integrated circuit device such as a single-chip microcomputer to be tested, 52 is an output terminal or an input / output terminal of the semiconductor integrated circuit device 51, 53 is a built-in memory built in the semiconductor integrated circuit device 51, and 54 is the same. Are registers built into the semiconductor integrated circuit device 51. Reference numeral 55 denotes an external memory connected to the semiconductor integrated circuit device 51. The semiconductor integrated circuit device 51 and the external memory 55 are connected by an address bus AB, a data bus DB, and a control signal line SL.

Next, the operation will be described. When measuring the output drive capability of the output terminal or the input / output terminal 52 of the semiconductor integrated circuit device 51 with the test circuit shown in FIG. 6, first, the mode is set in which the semiconductor integrated circuit device 51 can access the external memory 55. The semiconductor integrated circuit device 51 is operated in the mode. Then, a program for setting the internal memory 53, the register 54, the output terminal or the input / output terminal 52, and the like is written in the external memory 55, and the semiconductor integrated circuit device 51 operates according to the program to output the output terminal or the input / output terminal 52. The input / output terminal 52 is set. Since the output terminal or the input / output terminal 52 of the semiconductor integrated circuit device 51 is set as described above, when a new semiconductor integrated circuit device 51 is developed, the type and size of the internal memory 53, the configuration of the register 54, and the like. Each time the number or function of the output terminal or input / output terminal 52 is different,
It is necessary to change the program to be written in the external memory 55 and create it.

[0004]

Since the conventional semiconductor integrated circuit device is configured as described above, when measuring the output drive capability of the output terminal or the input / output terminal 52 of the semiconductor integrated circuit device 51, a new method is required. Each time a semiconductor integrated circuit device is developed, it is necessary to change the program to be written in the external memory 55, and there is a problem that improvement in efficiency in the development and evaluation of a shipping test program for the semiconductor integrated circuit device cannot be expected. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor integrated circuit device capable of improving the efficiency in measuring and evaluating the capability of an output driver of an output terminal or an input / output terminal. With the goal.

[0006]

A semiconductor integrated circuit device according to the present invention comprises: a test input terminal for inputting a signal for measuring and evaluating the capability of an output driver of an output terminal and an input / output terminal; Based on the signal input from the input terminal, generate and output test output data that determines the output from the output driver of the output terminal and the input / output terminal, and output the test output data from the output terminal and the input / output terminal. A test control logic for generating and outputting a control signal for obtaining an output, a test output data holding circuit for holding the test output data output from the test control logic, and a test output data holding circuit The output is simultaneously obtained from all of the output terminals and the input / output terminals based on the test output data and the control signal. It is obtained by so and a selection switch circuit for.

A semiconductor integrated circuit device according to the present invention is based on a control signal output from a test control logic.
An input / output selection switching circuit that invalidates a set value output of an input / output setting register that sets an input / output terminal to an input terminal or an output terminal and sets the input / output terminal to an output terminal, based on the control signal, A test held by a test output data holding circuit to all output drivers of the output terminals while disconnecting the connection between the output bus and all output drivers of the output terminals set by the input / output selection switching circuit and the data bus. A selection switching circuit includes a data bus selection switching circuit that can supply output data, and a port selection switching circuit that switches the port of the output terminal to active.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit block diagram showing a main part of a semiconductor integrated circuit device according to the first embodiment. In FIG. 1, reference numeral 100 denotes a semiconductor integrated circuit device which is, for example, an 8-bit single-chip microcomputer. Reference numeral 1 denotes a test control logic circuit (test control logic), and reference numeral 2 denotes one of an internal clock CLK of the semiconductor integrated circuit device 100 and a test clock output from the test control logic circuit 1 (hereinafter, referred to as test CLK). Is selected by the switching signal S1 output from the test control logic circuit 1. Reference numeral 3 denotes a register (test output data holding circuit) used for a measurement evaluation test of the capability of the output driver of the output terminal or the input / output terminal, which is an 8-bit register in this embodiment, but is a 1-bit register. There may be.

Reference numeral 4 denotes an output port, and 5 denotes an input / output port. Reference numeral 6 designates a switching signal S2 output from the test control logic circuit 1 to the bit data output signal line 32 from which one bit data set in the register 3 is output or the bit line DB7 at the uppermost position of the data bus. And the output bit terminal P at the highest level of the output port 4
This is a selection switching circuit for connecting to the output driver of A7. 7 selects and switches either the bit data output signal line 32 or the bit line DB6 of the data bus 22 by the switching signal S2 output from the test control logic circuit 1, and outputs the output bit terminal PA6 of the output port 4. Is a selection switching circuit for connecting to the output driver. Similarly, 8 selects and switches one of the bit data output signal line 32 and the bit line DB5 of the data bus 22 by the switching signal S2 output from the test control logic circuit 1, and the output bit terminal PA5 of the output port 4 Is a selection switching circuit for connecting to the output driver. DB4
Each of the following bit lines of the data bus 22 is also connected to the output driver of the corresponding output bit terminal of the output port 4 by selecting one of the bit lines output from the bit data output signal line 32. A selection switching circuit is provided.

Reference numeral 9 designates one of the bit data output signal line 32 and the uppermost bit line DB7 of the data bus by using the switching signal S2 output from the test control logic circuit 1 for switching. This is a selection switching circuit for connecting to the output driver of the most significant output bit terminal PA7. 10 is a bit data output signal line 32
And the bit line DB6 of the data bus 22 are selected and switched by a switching signal S2 output from the test control logic circuit 1, and are connected to the output driver of the output bit terminal PA6 of the input / output port 5. It is a switching circuit. Reference numeral 11 similarly selects and switches one of the bit data output signal line 32 and the bit line DB5 of the data bus 22 by the switching signal S2 output from the test control logic circuit 1, and the output bit terminal of the input / output port 5. P
A selection switching circuit for connecting to the output driver of A5. In addition, as with the output port 4, one of the bit lines of the data bus 22 below the DB 4 is also connected to the corresponding output bit terminal of the input / output port 5. A selection switching circuit for making connection to the output driver is provided.

Reference numeral 12 denotes a selection switching circuit for invalidating the select signal 24 for selecting the output port 4 and forcibly selecting the output port 4 by the signal S3 output from the test control logic circuit 1. Reference numeral 13 denotes a selection switching circuit for invalidating the select signal 25 for selecting the input / output port 5 and forcibly selecting the input / output port 5 by the signal S3 output from the test control logic circuit 1.

Reference numeral 14 denotes an input / output setting register for setting whether the input / output port 5 is to be used as an input port or an output port. This is a selection switching circuit for forcibly setting the input / output port 5 as an output port by a signal S3 output from the logic circuit 1.

Reference numeral 16 denotes a test input terminal provided in the semiconductor integrated circuit device.
The test circuit of the semiconductor integrated circuit device operates by inputting a predetermined signal to the semiconductor integrated circuit device. The test input terminal 16 may be provided in a plural number.
Test output data to be output to the selection control circuit 2 and signals for enabling the test control logic circuit 1 to generate the signals S1, S2, and S3 are input from the test input terminal 16.

FIG. 2 is a circuit diagram showing the configuration of the selection switching circuit 2, FIG. 3 is a circuit diagram showing the configuration of the selection switching circuits 12 and 13, and FIG. 4 is a selection switching circuit 6, 7, 8, 9, 10, 10 FIG. 5 is a circuit diagram showing a configuration of the selection switching circuit 15. The buffer in each of these circuits has a control terminal, and functions as a buffer circuit when an 'H' level signal is input to the control terminal. Further, when a signal at the "L" level is inputted to the control terminal, the output becomes high impedance, and the circuit to the input side is cut off.

Next, the operation will be described. When a signal for operating the test circuit is input from the test input terminal 16, a signal S is output from the test control logic circuit 1.
1, a signal S2 and a signal S3 are output. This signal S1,
The signal S2 and the signal S3 are “H” level signals. As a result, the clock supplied to the register 3 is switched from the internal clock CLK to the test CLK by the signal S1 output to the selection switching circuit 2. In this state, the test output data is output from the test control logic circuit 1 to the register 3 and the test CLK is output.
Is output to the register 3 via the selection switching circuit 2. The register 3 captures the test output data at the transition edge of the test CLK, and “1” is set in the register 3 as the least significant bit, for example. The test output data set as the least significant bit is output to the bit data output signal line 32.

On the other hand, the signal S2 output from the test control logic circuit 1 is output to the selection switching circuits 6 to 11 having the circuit configuration shown in FIG. The bit data output signal line 32 is separated from the output driver of the output port 4 in a circuit.
To the output driver of the output bit terminal PA7 of the output port 4. Similarly, in the selection switching circuit 7, the bit data output signal line 32 is connected to the output driver of the output bit terminal PA6 of the output port 4. Similarly, in the selection switching circuit 8, the bit data output signal line 32 is connected to the output port 4
And the bit data output signal line 32 is connected to the output driver of each output bit terminal of the output port 4. The same applies to the input / output port 5. The bit data output signal line 32 is connected to the output driver of each output bit terminal of the input / output port 5.

At this time, the signal S2 is supplied to the selection switching circuit 1
5, the selection switching circuit 15 shown in FIG. 5 invalidates the data set in the input / output setting register and outputs a signal S2 different from the data set in the input / output setting register to the input / output port 5. To an input port / output port switching circuit (not shown) to fix the input / output port 5 to an output port. On the other hand, when the signal S3 is output to the selection switching circuits 12 and 13, the selection switching circuits 12 and 13 shown in FIG. 3 select "unselected" supplied to the output port 4 and the input / output port 5. The signal S3, which becomes a select signal indicating “selection” by invalidating the signal, is used to select / not-show / select the output port 4 and the input / output port 5.
The output is output to the non-selection switching circuit, and the output port 4 and the input / output port 5 are set to the “selected” state.

As a result, from the output port 4, the test output data "1" set in the register 3 is output from each output bit terminal via the output driver. Also,
The input / output port 5 is fixed to an output port, and the test output data "1" is output from each output bit terminal via an output driver. Then, based on the test output data simultaneously output from each of these output ports, the output terminals of the output port 4 and the input / output port 5 or the capability of the output driver of the input / output terminal is measured and evaluated.

As described above, according to the first embodiment, the capability of the output driver of the output port 4 and the input / output port 5 of the semiconductor integrated circuit device 100 or the output driver of the input / output terminal, such as VOH and ICC-Leak, is provided. The measurement and evaluation can be performed simultaneously by the 1-bit test output data "1" set in the register 3 without inputting the program operation only by inputting a test signal from the test input terminal 16, and the capability measurement is performed. There is an effect that a semiconductor integrated circuit device that can improve the efficiency in performing the evaluation and also reduce the test time can be obtained. Also, even when developing a new semiconductor integrated circuit device such as a single-chip microcomputer, even if the type of internal memory, the size and the configuration of various registers, and even the number and functions of the terminals are different,
The capability measurement / evaluation can be performed in the semiconductor integrated circuit device itself without creating a test program, and there is an effect that the work efficiency of the capability measurement / evaluation can be improved and the test time can be reduced.

In the embodiment described above, one-bit test output data "1" is set in register 3, but test output data "0" may be set. With this configuration, it is possible to measure and evaluate the performance of the output terminals of the output port 4 and the input / output port 5 or the output driver of the input / output terminal, such as VOL and ICC-Leak.

The test output data set in the register 3 may be switched to "1" or "0" by a test signal input from the test input terminal 16. The register 3 may be a simple test-only latch circuit that does not require a clock.

[0022]

As described above, according to the present invention, a signal for measuring and evaluating the capability of the output driver of the output terminal and the input / output terminal is input from the test input terminal, and the signal is generated based on the signal. Generating and outputting test output data and a control signal by a test control logic, holding the test output data, controlling a selection switching circuit based on the control signal, and responding to the held test output data. Output terminals and the input / output terminals, so that output signals for all of the output terminals and the input / output terminals are obtained by the signal input from the test input terminal regardless of the program operation. There is an effect that the measurement and evaluation of the ability can be performed efficiently and in a short time.

In addition, even if the type, size and register configuration of the built-in memory and the number and functions of the terminals are different for each semiconductor integrated circuit device to be measured and evaluated for the capability of the output driver, the measurement and evaluation are not performed. The performance of the output driver for all of the output terminals and input / output terminals can be measured and evaluated in the semiconductor integrated circuit device itself to be measured and evaluated without creating a program. There is an effect that shortening can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a configuration of a selection switching circuit of a main part of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration of a selection switching circuit of a main part of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a circuit diagram showing a configuration of a main part selection switching circuit of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a circuit diagram showing a configuration of a selection switching circuit of a main part of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a block diagram showing a configuration of a test circuit when measuring output drive capability of an output terminal or an input / output terminal in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 test control logic circuit (test control logic), 2, 6 to 13 selection switching circuit, 3 registers (test output data holding circuit), 16 test input terminals,
22 data bus, 100 semiconductor integrated circuit device.

Claims (2)

[Claims] A test input terminal for inputting a signal for measuring and evaluating the capability of an output driver of an output terminal and an input / output terminal; and a signal input from the test input terminal.
A test for generating and outputting test output data for determining the output from the output driver of the output terminal and the input / output terminal, and generating and outputting a control signal for obtaining the output from the output terminal and the input / output terminal Control logic, a test output data holding circuit that holds the test output data output from the test control logic, and a test output data and a control signal that are held by the test output data holding circuit. And a selection switching circuit for simultaneously obtaining the output from all of the output terminal and the input / output terminal. 2. The selection switching circuit according to claim 1, wherein a setting value output of an input / output setting register for setting an input / output terminal to an input terminal or an output terminal is invalidated based on a control signal output from the test control logic. An input / output selection switching circuit for setting a writing output terminal to an output terminal; and, based on the control signal, all output drivers and data buses of the output terminal set by the output terminal and the input / output selection switching circuit. A data bus selection switching circuit that enables the test output data held by the test output data holding circuit to be supplied to all the output drivers of the output terminal while disconnecting the connection of the output terminals; and a port selection that switches the port of the output terminal to active. 2. A switching circuit, comprising:
13. The semiconductor integrated circuit device according to claim 1.