JPH0360180B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monolithic circuit in the microwave band, and particularly to a power amplifier circuit using a semi-insulating compound semiconductor substrate.

With recent advances in semiconductor technology, monolithic circuits integrated on semiconductor substrates have come to be used for power amplifier circuits in the microwave band. High-output FETs are increasingly being used in power amplifier circuits. However, power amplifier circuits consume a lot of power, so
There is a problem in that high output cannot be expected unless the thermal resistance of the FET is lowered to keep the amount of heat generated low.

FIG. 1 is a sectional view of an example of a conventional output FET.

An n-type operating layer 1 is formed on the upper surface of a semi-insulating semiconductor substrate 11.
2 is provided, and a source electrode S, a drain electrode D, and a gate electrode G are provided thereon. Board 11
A through hole 13 is formed in the through hole 13, and the source electrode S is connected to a ground conductor 14 provided on the back surface of the substrate via a metal layer 15 formed on the inner surface of the through hole 13.

In a high-output FET, it is preferable that the semi-insulating semiconductor substrate 11 be thinner for the following reasons. First, by making the substrate thinner, thermal resistance is reduced, and temperature rise due to heat generation due to DC input is suppressed.
Furthermore, the thinner the substrate, the smaller the source inductance in the portion of the through hole 13, improving the gain and output power. Furthermore, if the board is thick, the through hole 1
The opening of No. 3 becomes large, making it difficult to manufacture.
For these reasons, ordinary high-power FETs
The thickness of the substrate 11 is reduced to about 25 to 50 μm, and a through hole 13 is formed from the surface of the substrate 11 in order to reduce the opening in the source electrode S portion.

When a monolithic amplifier circuit is constructed using such a thin substrate 11, the loss of the matching circuit formed on the substrate increases. Therefore, in the current monolithic amplifier circuit, the thickness of the substrate is 150 to 200 μm.
This suppresses the loss of the matching circuit to a small level, but this has the drawback that the source electrode in the area where the through hole 13 is formed is large, and the thermal resistance is large, which limits the ability to increase the output of the amplifier circuit. Ta.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide a monolithic circuit with low thermal resistance, low source inductance, and low matching circuit losses.

According to the present invention, in a monolithic circuit in which a transistor and a matching circuit for the transistor are formed on one main surface of a compound semiconductor substrate, a region of the compound semiconductor substrate in which an operating layer of the transistor is formed is formed on the other main surface. a thin region is removed from the side, a through hole penetrating the compound semiconductor substrate is provided in the thin region, a ground conductor is provided on the other main surface of the compound semiconductor substrate including the thin region, and a ground conductor is provided on the other main surface of the compound semiconductor substrate including the thin region; A monolithic circuit is obtained, characterized in that the common electrode of the transistor is connected to the ground conductor via a metal layer formed in the through hole.

Next, embodiments of the present invention will be described using the drawings.

Figures 2a and 2b are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention.

First, as shown in FIG. 2a, a GaAs substrate 20
FET21 and DC cut capacitor 22 on top
A feedback circuit consisting of a feedback inductor 25 and a resistor 26, and a bias circuit consisting of an output matching inductor 24, a bias supply resistor 28, an RF shot capacitor 23, and a ground electrode 27 are formed. do. The feedback circuit and the output matching inductor 24 constitute an output matching circuit.

As shown in FIG. 2b, the area where the FET 21 and the ground electrode 27 are formed is thinned by etching the substrate 20. The through holes 29 are formed by etching from the surface of the substrate 20.
The ground conductor 30 is provided on the back surface of the substrate including the thinned portion, and the ground electrode 27 and the source electrode S of the FET 21 are connected to this ground conductor 30. In this embodiment, the ground electrode 27 is also made thinner.
When the ground electrode 27 is provided toward the edge of the substrate, the ground electrode portion does not necessarily have to be made thin because the ground electrode can be connected through the edge of the substrate.

To give an example of the dimensions, the thickness of the substrate 11 is 200 μm,
The thickness of the area where FET21 is formed is 50μ
m, and the area is 150 μm x 300 μm. In other words,
The bottom of FET21 is dug 150μm deep.

In this way, it is not easy to further provide the grounding through hole 30 in a place that has been partially dug deeply from the back surface, and the success or failure of the process largely depends on the order of processing.

In the usual method, a photoresist is first applied to the back surface, the photoresist is removed from the area where the through hole 29 is to be formed, and the through hole 29 is formed by chemically etching the substrate 20 using this photoresist as a mask. However, the substrate 2 with a thickness of 200 μm
When photoresist is applied to the substrate surface where a narrow area of about 150 x 300 μm where the FET 21 of 0 is formed is dug to a depth of 150 μm, the photoresist in the dug portion becomes very thick and uneven within the substrate surface. become. Therefore, it is difficult to expose and remove the photoresist in the dug portion uniformly and accurately. In addition, when forming through holes from the back surface, if the thickness of the substrate 20 is uneven within the surface, some of the through holes may remain without penetrating, or the upper surface of some of the through holes may become uneven. The opening becomes unnecessarily large, causing problems such as short circuit with the gate electrode G. Furthermore, if the photoresist mask becomes non-uniform as described above, an extra dimensional margin must be allowed for the upper electrodes (source electrode S and ground electrode).

Therefore, in this embodiment, a through hole is formed from the source electrode side to a depth equal to or greater than the thickness of the substrate to be thinned after this step, and then a metal layer is formed on the side surface of the through hole.
Only the lower part of the FET 21 and the ground electrode 27 are removed from the back surface to reduce the thickness to the desired thickness. In this example, in the process of thinning a part of the board from the back side of the board, the metal layer in the plane of the previously formed through hole is exposed, so the thickness of the board in the part to be thinned is determined by the depth of the through hole. It can be controlled. Therefore, the connection between the source electrode S or the ground electrode 27 and the back surface can be made reliably and easily. In this embodiment, the thermal resistance and source inductor are reduced by reducing the thickness of the substrate below the FET 21.
Moreover, by leaving the matching circuit portion thick on the substrate, a monolithic amplifier circuit can be obtained without increasing circuit loss.

In the above-mentioned through-hole formation process, by using anisotropic etching such as reactive ion etching, it is possible to make the side surfaces of the through-hole nearly vertical, and the opening in the source electrode S can also be kept small. I can do it.

As explained in detail above, according to the present invention,
By making the substrate thinner in the area where the FET is formed, a monolithic circuit with lower thermal resistance and lower source inductance and matching circuit loss can be obtained, which is highly effective.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of an example of a conventional output FET.
FIGS. 2a and 2b are a plan view and a sectional view of an embodiment of the present invention. 11... Semiconductor substrate, 12... Operating layer, 13...
...through hole, 14...ground conductor, 15...metal layer,
20...GaAs substrate, 21...FET, 22...
DC cut capacitor, 23...RF shot capacitor, 24...Output matching inductor, 2
5... Feedback inductor, 26... Resistor, 27... Ground electrode, 28... Resistor, 29...
Through hole, 30...Grounding conductor.

Claims (1)

[Scope of Claims] 1. In a monolithic circuit in which a transistor and a matching circuit for the transistor are formed on one main surface of a compound semiconductor substrate, the compound semiconductor substrate in a region where an operating layer of the transistor is formed is A thin region is removed from the surface side, a through hole penetrating the compound semiconductor substrate is provided in the thin region, and a ground conductor is provided on the other main surface of the compound semiconductor substrate including the thin region, A monolithic circuit characterized in that a common electrode of the transistor is connected to the ground conductor via a metal layer formed in the through hole. 2. The monolithic circuit according to claim 1, wherein the cross section of the through hole becomes smaller from one main surface side to the other main surface side of the compound semiconductor substrate.